Product Review
Synopsys gathers Virtio, VaST, and CoWare into Virtualizer
Ron Wilson7/19/2011 1:09 PM EDT
Comment
achimnohl
I agree that tools are becoming more application specific. In fact, Virtualizer ...
achimnohl
Virtualizer analysis tools cover the whole spectrum from software analysis to ...
Synopsys today announced release of the Virtualizer tool set: a virtual system prototyping platform that brings together tools the company acquired from Virtio (virtual prototyping for software development), VaST (subsystem models), and CoWare (hardware-software coverification).
The announcement is more than a simple rebranding of the acquired product lines, according to director of product marketing Marc Serughetti. Virtualizer includes the previous tools, but adds new models, assembles the capabilities into a single OSCI TLM 2.0-based environment, and provides links into Synopsys’s HAPS hardware prototyping system, instruction-set-level processor simulators, and analysis tools, including some third-party software debug and analysis products.
The concept, Serughetti said, is to create an environment in which a design team can assemble a virtual system prototype, including models at different levels of abstraction. Then designers can create whatever views of the system they need—behavioral, transaction-level, instruction-level, RT-level, or a mixture—to perform a simulation or analysis run.
Synopsys has added tools for model creation and debug, and also application-specific reference designs. Both are intended to get virtual system prototypes up and running quickly. There are also Virtualizer Development Kits: pre-configured subsets of the full Virtulaizer package for specific tasks such as software development, SoC verification, or system testing.
The announcement leaves out a great many details, such as what models are available, descriptions of the model-builder/debugger and various analysis tools, the mechanism for linking models at different levels of abstraction for simulation or—especially—analysis, and just how the user goes about instrumenting and controlling such a multimode prototype. It appears that the system may be assembled and controlled on a TLM 2.0 backplane, but that is not explicitly stated in the product materials.
What is clear is that Synopsys is attempting to meet the disparate needs of early software development and SoC architecture verification in the chip-design world, the needs of software developers working in the Linux/Android world, and the needs of system prototyping teams in specific applications such as automotive and aerospace, all from a single tool set. Given the tendency of tools to become application-specific as they move from conception into actual use, this could be a challenging and resource-consuming effort for the EDA giant. But clearly it is a move in concert with Cadence’s and Mentor’s increasing emphasis on system, and especially software, development needs. Virtualizer and some of the Development Kits are available now.
The announcement is more than a simple rebranding of the acquired product lines, according to director of product marketing Marc Serughetti. Virtualizer includes the previous tools, but adds new models, assembles the capabilities into a single OSCI TLM 2.0-based environment, and provides links into Synopsys’s HAPS hardware prototyping system, instruction-set-level processor simulators, and analysis tools, including some third-party software debug and analysis products.
The concept, Serughetti said, is to create an environment in which a design team can assemble a virtual system prototype, including models at different levels of abstraction. Then designers can create whatever views of the system they need—behavioral, transaction-level, instruction-level, RT-level, or a mixture—to perform a simulation or analysis run.
Synopsys has added tools for model creation and debug, and also application-specific reference designs. Both are intended to get virtual system prototypes up and running quickly. There are also Virtualizer Development Kits: pre-configured subsets of the full Virtulaizer package for specific tasks such as software development, SoC verification, or system testing.
The announcement leaves out a great many details, such as what models are available, descriptions of the model-builder/debugger and various analysis tools, the mechanism for linking models at different levels of abstraction for simulation or—especially—analysis, and just how the user goes about instrumenting and controlling such a multimode prototype. It appears that the system may be assembled and controlled on a TLM 2.0 backplane, but that is not explicitly stated in the product materials.
What is clear is that Synopsys is attempting to meet the disparate needs of early software development and SoC architecture verification in the chip-design world, the needs of software developers working in the Linux/Android world, and the needs of system prototyping teams in specific applications such as automotive and aerospace, all from a single tool set. Given the tendency of tools to become application-specific as they move from conception into actual use, this could be a challenging and resource-consuming effort for the EDA giant. But clearly it is a move in concert with Cadence’s and Mentor’s increasing emphasis on system, and especially software, development needs. Virtualizer and some of the Development Kits are available now.
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achimnohl
7/22/2011 5:55 PM EDT
Hi Ron, thanks for the write-up on Virtualizer. I saw you had some questions so here is a brief reply for your readers. They can contact us for more details.
TLM library availability is definitely a strength for Virtualizer. Virtualizer supports a broad model library and reference design portfolio with more than 500 models available from Synopsys. These models include processor cores, interconnects, peripherals as well as complete reference designs running entire software stacks. Synopsys provides support for a wide range of popular processor architectures including ARM, MIPS, PowerPC, SH, V850, Tensilica, DSPs as well as peripheral IP models from DesignWare and ARM PrimeCell. In addition an extensive set of APIs enable developers to incorporate their own models for simulation, debugging and analysis in Virtualizer. Most models are SystemC TLM-2.0, however Virtualizer supports additional TLM protocols as well, including AMBA based, OCP-IP based, and customer-specific TLMs.
Multicore software debug and analysis with Virtualizer is non-intrusive. In order to manage platforms with many CPU subsystems from an SW developer perspective, we provide a dedicated debug server that allows orchestration of 3rd party debuggers that can be attached to the CPUs in the virtual prototype (VP). Thus, all debuggers can co-operate (rather than freezing) in scenarios where multiple software entities need to be debugged at the same time. Furthermore, we provide a central debug and control cockpit that allows the global control and inspection of the entire VP. Complementing SW debuggers which are CPU specific, this provides a platform level view and exposes all relevant registers/signals/memories and disassembly of all CPUs. Virtualizer enables this out of the box. The user doesn’t have to add any instrumentation to their code, they can run the same unmodified binaries on the VP that will run on the actual hardware.
Achim Nohl, Solution Architect, Synopsys
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achimnohl
7/22/2011 5:57 PM EDT
Virtualizer analysis tools cover the whole spectrum from software analysis to platform hardware analysis. Each analysis view is tailored to a specific purpose, such as software analysis, HW/SW interface analysis, memory analysis, power analysis and more. All data is stored in a single database so that any type of analysis can be easily correlated. Analysis instrumentation is based on industry standard TLM-2.0 interfaces and the open SystemC Modeling Library (SCML2) APIs from Synopsys. This makes modeling much easier and efficient through the concept of modeling objects and reusable design patterns. Moreover, the TLM processor models in our library are further instrumented to expose IP-specific performance counters and other data for debug and performance analysis. The modeler can also use our instrumentation framework to visualize any relevant information from their VP - and its operating environment - in combination with Virtualizer analysis views. For example, they can create a power model of a modem which is driven by software but does not exist as a functional model. (We recently did a webinar on this topic).
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achimnohl
7/22/2011 5:58 PM EDT
I agree that tools are becoming more application specific. In fact, Virtualizer enables VPs to be made aware of the specific characteristics of user software stacks, and associated software development tasks. For example, Virtualizer software analysis can be made OS-aware so that the user understands the system behavior at a much higher level of abstraction than just tracing functions. The same idea can be applied to the full software stack layered upon the OS kernel, and across multiple cores. As a result, Virtualizer analysis is aware of the fact that the CPU is running Android and clearly visualizes important data such as the Android software logging, Java/native code interfacing, and Java interpreter at the right abstraction level. In a multi-million line software stack, the challenge is to understand the relation between the user/environment-initiated activities and the resulting HW/SW behavior. Simple hardware signal tracing and function tracing are far too detailed to understand this. Because every software stack is different, Virtualizer provides APIs that allow the user to easily and stepwise tailor the analysis to what is needed. We have example analysis kits for Android Gingerbread 2.3.4 as well as Linux 2.6.x and others, to help guide them.
Achim Nohl, Solution Architect, Synopsys
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