Digital Core Design updates on chip debug

In a modern system-on-chip, traditional measurement instrumentation does not have access to all of the pins necessary to provide good visibility and debug. For that reason, on-chip instrumentation has become a necessity. I wrote about this recently in EDN “Is there a market for on-chip instrumentation?” and also reported about the availability of an IJTAG tutorial from ASSET InterTech just last week.

Today, I want to mention a new product from Digital Core Design called DoCD. It is a debugging system consisting of three blocks: Debug IP Core, Hardware Assisted Debugger (HAD2) and Debugging Software. DoCD v.6.01 offers real time, non-intrusive debug capability, enabling a pre-silicon validation and post-silicon, on chip software debugging. DoCD allows hardware breakpoints, trace, variables watch and multi C sources debugging. It also enables display and modification of memory contents, processor and peripheral register windows, along with information tracing and ability to see the related C/ASM source code.
Complete DoCD system consists of three major parts:

• Hardware Assisted Debugger: Pendrive packaged - HAD2 is a small hardware adapter, that manages communication between the Debug IP Core (JTAG protocol) inside silicon and a USB port of the host PC, running DoCD Debug Software.
• Debug Software: is a Windows based application, compatible with all existing compilers and assemblers. The DS was designed to work in two major modes: software simulator and hardware debugger mode. They allow pre-silicon software validation in simulation mode and then, real-time debugging of developed software inside silicon - using debugger mode. Once loaded, the program may be observed in Source Window, run at full-speed, single stepped by machine or C-level instructions or stopped at any of the breakpoints.
• Debug IP Core: is a real-time hardware debugger, which provides an access to all chip registers, memories and peripherals, connected to the IP Core. It controls CPU work, by non-intrusive method. The Debug IP Core is provided as VHDL or Verilog source code, as well as CPLD/FPGA EDIF netlist.

The Debug IP Core, can be scaled to control gate count. The benefit is fewer gates - for lower use of power and core size, while maintaining necessary debug abilities. Typically, all of the features are utilized in pre-silicon debug (i.e. hardware debugging or FPGA evaluation), with less features inserted into final silicon.
 
More information can be found here

Brian Bailey – keeping you covered

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