Synopsys IC Validator updated for 20nm

Synopsys has released IC Validator 2012.06, a physical verification platform for advanced process nodes. IC Validator 2012.06 offers new technologies that enable physical signoff verification at advanced process nodes with qualified rule decks by leading foundries.

New additions to the In-Design flow, targeted for 20nm and below, include DPT and pattern matching technology. This latest release of IC Validator also offers a significant performance boost for verifying large and complex 20-nm designs. IC Validator can enable engineers to parallelize design rule checks (DRCs) on 64 processing cores and beyond

IC Validator 2012.06 introduces several new capabilities:

• Double Patterning: The limitations of current lithographic technology require layout to be split into two masks of alternating structures. IC Validator features a native decomposition ("coloring") engine. IC Validator can perform decomposition checks during design and can also drive automatic fixing of violations with IC Compiler via the In-Design technology. IC Validator can also perform the final signoff quality check alongside the final design rule check.
• Pattern Matching: Occasionally layout patterns can generate lithography hotspots, leading to accidental open or short connections. IC Validator's patented pattern-matching technology augments DRC with 2D multi-shape pattern analysis for detection of manufacturing hotspots. It can also drive automatic fixing of these hotspots with IC Compiler. Leading manufacturers will thus be able to achieve better process margins and higher yields for the 20-nm process node.

More information available at:

http://www.synopsys.com/Tools/Implementation/PhysicalVerification/Pages/ICValidator-ds.aspx

Brian Bailey – keeping you covered

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