The folks at Aldec
have just announced the release of their mixed language advanced verification platform, Riviera-PRO 2012.10
. The release delivers numerous stability and performance improvements, support for the latest versions of industry-standard SystemVerilog verification libraries, new language constructs, new debugging tools, and improved interfaces to other industry leading EDA tools.
Riviera-PRO delivers a 20% VHDL simulation performance gain over previous releases. “We keep developing and delivering not only new productivity features, but also innovative core engine optimizations to boost simulation performance in VHDL and SystemVerilog to support the complexity and capacity of today’s designs,”
said Mariusz Dykierek, Aldec R&D Project Manager. “Easy-to-use debugging tools and a powerful mixed language simulation engine are in high demand. Aldec continues to help our customers reduce design cost and time and bring their products to market quickly.” Highlights of Riviera-PRO 2012.10:
Core Simulation Engine
Framework and Productivity
- Simulation performance improvements – VHDL simulation now up to 20% faster!
- New language constructs in SystemVerilog’2009 and VHDL’2008
- Support for the latest verification libraries – UVM 1.1c, SystemC 2.3.0, OS-VVM
- Increase Stability on large multi-million gate designs
- Waveform enhanced for displaying of composite objects (virtual arrays)
- Possibility to rename objects in the waveform, and context search
- Additional operations using the drag-n-drop method
Complete list of new features and enhancements
- The new way to use MATLAB co-simulation interface – Invoke Riviera-PRO from MATLAB
- The latest precompiled simulation libraries for Altera and Xilinx FPGAs
- Compatibility with the latest release of Xilinx Vivado Design Suite supporting Virtex-7
- FSDB updated to the version 5.0 – Compatible with Verdi 2012.07
Riviera-PRO 2012.10 Release Notes“What’s New” presentation
Riviera-PRO 2012.10 What's NewAvailability
Riviera-PRO 2012.10 is available today. Click Here
to download the latest release. Current customers with valid maintenance receive the release at no additional cost.
If you found this article to be of interest, visit Programmable Logic Designline
where – in addition to my Max's Cool Beans
blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here
to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).