Product Review
Digital Blocks extends I2C controller IP core family
Clive Maxfield1/10/2013 12:53 PM EST
The folks at Digital Blocks, developers of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, and FPGA developers with embedded processor and associated peripherals requirements, have announced the extension of their DB-I2C-MS / DB-I2C-M / DB-I2C-S I2C controller IP core family, with the following enhanced system-level features and integration capabilities:
The DB-I2C family contains the usual I2C compliant features: Multi-Mastering, Clock Synchronization, Arbitration, SCL held low by Slave, Repeated Start, 7/10-bit addressing, and General Call capabilities as well as 100 Kbs, 400 Kbps, and 1 Mbps I2C bus speeds.
The DB-I2C IP Core Family is offered as follows:
Price and availability
The DB-I2C IP Core Family is available immediately in synthesizable Verilog, along with synthesis scripts, a simulation test bench with expected results, datasheet, and user manual. For further information, product evaluation, or pricing, please visit Digital Blocks at www.digitalblocks.com
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
- CPU Interface via parameterized FIFO with support for APB / AHB / AXI / AXI-lite / Avalon / Qsys interconnect fabrics
- DMA transfer between the I2C Bus and Memory (SDRAM / SRAM / FLASH)
- Direct interface to user Registers within ASIC / ASSP / FPGA, for Master/Slave transfer across the I2C Bus
- Remote Configuration of a Digital Blocks’ I2C Slave by an I2C Master
- Enhanced SCL / SDA spike filtering capabilities
- Enhanced Repeated Start capabilities
- Control Unit which completely off-loads the I2C transfer from the CPU
The DB-I2C family contains the usual I2C compliant features: Multi-Mastering, Clock Synchronization, Arbitration, SCL held low by Slave, Repeated Start, 7/10-bit addressing, and General Call capabilities as well as 100 Kbs, 400 Kbps, and 1 Mbps I2C bus speeds.
The DB-I2C IP Core Family is offered as follows:
Price and availability
The DB-I2C IP Core Family is available immediately in synthesizable Verilog, along with synthesis scripts, a simulation test bench with expected results, datasheet, and user manual. For further information, product evaluation, or pricing, please visit Digital Blocks at www.digitalblocks.com
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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