Digital Core Design's tiny UART IP core – DuART

"Small is beautiful," as the old saying goes. This can be seen in Digital Core Design's DμART – a soft core implementation of a Universal Asynchronous Receiver/Transmitter (UART) for use in ASICs / ASSPs / SoCs and FPGAs.

In addition to performing serial-to-parallel conversion on data characters received from a peripheral device or a modem, the DμART can also perform parallel-to-serial conversion on data characters received from the CPU.

The CPU itself can read the complete status of the UART at any time during functional operation. Reported status information includes the type and condition of the transfer operations being per-formed by the UART, as well as any error conditions, like overrun or framing.

"The DμART includes also a programmable baud rate generator," says Jacek Hanke, CEO at Digital Core Design, "which is capable of dividing the timing reference clock input by divisors of 1 to (2¹⁶ - 1) and producing a 16 × clock for driving the internal transmitter logic." Provisions are also included to use this 16 × clock to drive the receiver logic. The newest UART Core from Digital Core Design has also been equipped with a processor-interrupt system. Thanks to this, interrupts can be programmed according to the user's requirements, thereby minimizing the computing required to handle the communications link.

The DμART core is perfect for applications where the UART and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC / ASSP / SoC or FPGA. DCD’s solution is also suitable for a standalone implementation, in which several UARTs are required to be implement-ed inside a single chip and driven by some off-chip devices also.

Key features are as follows:

• Majority Voting Logic
• Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data
• In a UART mode, receiver and transmitter are double buffered, to eliminate the need for precise synchronization between the CPU and serial data
• Independently controlled transmit, receive, line status, and data set interrupts
• 16 bit programmable baud generator
• False start bit detection
• Line break generation and detection. Internal diagnostic capabilities (loop-back controls for communications link fault isolation; overrun, framing error detection)
• Full prioritized interrupt system controls
• Technology independent HDL Source Code
• Fully synthesizable static design with no internal tri-state buffers

Click Here for more information and to see a datasheet.
 

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