DCD's DQSPI IP core – quad-performance SPI

The DQSPI IP core from Digital Core Design (DCD) is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or a slave device with data rates as high as CLK/2, when other vendors’ solutions offer just CLK/8.

This quad SPI has been designed to offer the fastest available operations for any serial memory. Moreover, the DQSPI has been design to operate with every 8, 16 or 32 bit processor available on the market.

The DQSPI is a fully configurable SPI master/slave device, which allows users to configure the polarity and phase of the serial clock (SCK) signal. This allows the microcontroller to communicate with fast serial SPI memories and serial peripheral devices. Moreover, it’s capable of inter-processor communications in a multi‐master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the four serial data lines. "In the Single SPI mode, data is simultaneously transmitted and received," says Jacek Hanke, CEO in Digital Core Design. "In DUAL and QUAD SPI modes, data is shifted in or out on two or four data lines, simultaneously."


Special clock control logic facilitates the selection of clock polarity, phase, and a choice of four fundamentally different clocking protocols to accommodate most synchronous serial peripheral devices available. When the SPI is configured as a master, software is used to select bit rates for the serial clock. Error‐detection logic is included to support inter-processor communications.

A write‐collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple‐master mode‐fault detector automatically disables DQSPI output drivers if more than one SPI device simultaneously attempts to become bus master.

The DQSPI supports two DMA modes: single transfer and multi‐transfer. These modes allow the DQSPI to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers.

The DQSPI is fully customizable, which means it can be delivered in the exact configuration to meet users’ requirements.

DQSPI Features:

• Operates with 8, 16, and 32-bit CPUs
• Full duplex synchronous serial data transfer
• DMA support
• Support for 32, 16, and 8-bit systems
• Support for various bus standards
• Supports single, dual, and quad SPI transfers
• Multimaster system supported
• Optional FIFO size extension (128, 256, 512B)
• Up to 8 SPI slaves can be addressed (Software Slave Select Output – SSO – selection; automatic Slave Select outputs assertion during each byte transfer)
• System error detection
• Interrupt generation
• Various bit rates supported
• Bit rate in fast SPI Mode 1/2 CLK
• Four transfer formats
• Simple SPU and DMA interface
• Fully synthesizable, static synchronous design with no internal tri‐states

The following table shows results for DQSPI performance in Altera's devices after place-and-route (all key features have been included):


Please visit www.dcd.pl for more information.

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