Earlier this week, Cadence announced some new intellectual property (IP) that aims to streamline the incorporation of DDR4 memory into system on chip (SoC) designs. I spoke with Neil Hand, group director, marketing, SoC realization for Cadence Design Systems, at length about the announcement.
First, I learned that what is going on at Cadence is a lot more than just supporting the emerging DDR4 standards. In fact, the company has reorganized its entire company around a new hierarchy to fully support design up through the system level. They have dubbed the program EDA360, and it incorporates computing (in terms of embedded CPUs and software), interface (standards-based I/Os) and now memory and storage (assisted by the acquisition of Denali Software Inc. last year).
No one disputes that IP is used in computing and interfaces. But memory, really?
"Today, memory and storage has some IP focus to it, but it has largely been managed in house," admits Hand. "Now is the time people are beginning to look at memory and storage from an IP perspective. This is becoming a key focus area for the IP industry."
Every designer knows that selecting the wrong memory will adversely affect the overall system performance. And, memory complexity is increasing. So, how do you optimize? Hand notes that there are diverse requirements in SoCs. For example, some need low latency and others are working in more 'human' time. The challenge with 'in house' solutions is always the same: optimization requires in-house expertise and keeping up with emerging standards. As a further complication, these resources would likely be better spent on differentiating the final design. So, the time is ripe for memory IP. Enter Cadence.
DDR4 is an emerging memory standard that aims at a wide range of implementations for different systems. For system integrators to take full advantage of DDR4 when it becomes finalized, they need to be working with it now. The new standard features double the bandwidth and reduced voltage and power as compared to DDR3. Samsung
have both announced DDR4 products.
Cadence has announced availability of DDR4 IP, and it hopes this will allow SoC designers to get a jump on designs and not have to play catch up with the large system and PC designers. The company will continue to track the standard as it evolves, and will make the necessary adjustments to its IP along the way.
The Cadence offering includes the DDR4 controller IP, DDR4 hard and soft PHY IP, memory models, verification IP, and a design-in kit.
Figure 1: Cadence DDR4 IP offering aims for an end-to-end solution.
DDR4 controller IP
The DDR4 controller IP meets the speed grades of DDR4, and it also supports all previous memory standards. Cadence works directly with each customer to deliver a uniquely configured controller that includes exactly the performance and features needed--from MP3 players to supercomputers. In some cases, the company reports that it can turn a tested and customized design in as little as 24 hours. Optimization examples include bandwidth optimization through traffic management, or power optimization and traffic sensing (allows the memory controller to control the DRAM power state based on real-time memory activity).
Here are the key features of the controller IP:
- All DDR1/2/3/4, LPDDR1/2, Wide I/O memories
- DDR2/3/4 DIMM support
- ECC and BIST support
- Fully DFI compliant
Configured using a GUI, Cadence's soft PHY supports speed grades up to DDR-3200 and allows the customer to select the floor plan, routing, and I/O. Cadence's DDR hard PHY has initial support for DDR-2400 with a roadmap to DDR-3200. According to Hand, Cadence's hard PHY is more flexible than competing products. "We 'hard in' key pieces of the IP, and then we left some of the other areas soft, leaving a degree of flexibility at the logical level."
Cadence has also developed a new design-in kit for DDR that allows designers to put DDR into designs before committing to an implmentation. "They can explore different memory topologies and see what meets their signal integrity requirments, all before committing to a final silicon implementation. The aim here is to lower the overall risk of using DDR in their design," notes Hand.
All of these pieces fit together nicely in support of Cadence's EDA360 strategy. The company's aim is to deliver a "very broad-based comprehensive solution for storage." Please use the comments section below to tell us if you agree, or if you have any questions...
DDR4 controller IP, verification IP and memory models are available now, and supported by both Cadence and third-party design tools and methodologies. A soft DDR4 PHY is expected to be available this quarter, while a hard PHY solution for 28-nm TSMC geometries is expected to be available by Q3 2011
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