Product Review
Design West: Express Logic's ThreadX RTOS supports both symmetric and asymmetric multiprocessing for multicores
Toni McConnel3/24/2012 7:03 PM EDT
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Express Logic, Inc., has announced that the ThreadX RTOS now is available for multicore systems in both Symmetric Multiprocessing (SMP) or Asymmetric Multiprocessing (AMP) modes, giving developers ultimate flexibility for using ThreadX in both homogeneous or heterogeneous systems.
With homogeneous processors, such as ARM’s MPCore, Xilinx Zynq, and MIPS 34K and 1004K, each processor runs the same code from a single copy in memory. Homogeneous processors also can be used in an AMP mode, where each processor is more independent, and can run different code from its own local memory. Heterogeneous processors, such as TI’s OMAP series, and ARM’s new big.LITTLE architecture, do not use SMP mode since their processors generally cannot run identical instructions from the same copy in memory and they almost always run in AMP mode.
ThreadX/SMP optimizes processor efficiency with automatic load balancing and/or program-directed, thread-processor affinity. Developers can exploit this functionality to run applications virtually without regard to the multiple processors in the system or to explicitly control the use of each processor. ThreadX/SMP automatically runs application threads on any available processor, transparently mapping a multithreaded, real-time system onto a multicore architecture.
In AMP mode, on homogeneous or heterogeneous multicore systems, ThreadX runs on one or more processors, generally from a processor’s local memory, with separate copies for each processor. If the system is made up of heterogeneous processors, then each copy of ThreadX is different, built for operation on a particular processor architecture. For example, TI’s OMAP combines an ARM core and a TI DSP core in a heterogeneous multicore system that could run ThreadX on each processor, or on just one with a different RTOS on the other. Similarly, the new Xilinx Zynq (a two-processor, homogeneous FPGA) could run ThreadX on one processor, while running Linux on the other. Interprocessor coordination is provided by the application using a shared memory mailbox and/or using the PolyCore Software’s MCAPI-compliant Poly-Messenger communications system. This provides the benefits of both operating systems, rather than trying to stretch either one to handle all system functions.
In SMP mode, ThreadX/SMP supports ARM’s MPCore, MIPS’ 34K and 1004K, and Analog Devices’ Blackfin BF561. In AMP mode, ThreadX supports the Xilinx Zynq dual-Cortex-A8 architecture, as well as virtually any heterogeneous architecture.
Shipping and Availability
ThreadX/SMP is available in full source-code form, royalty-free, with project license prices starting at $15,500.
For more information visit Express Logic's Design West Booth 1515, go to this page, call 1-858-613-6640, or e-mail info@expresslogic.com.
With homogeneous processors, such as ARM’s MPCore, Xilinx Zynq, and MIPS 34K and 1004K, each processor runs the same code from a single copy in memory. Homogeneous processors also can be used in an AMP mode, where each processor is more independent, and can run different code from its own local memory. Heterogeneous processors, such as TI’s OMAP series, and ARM’s new big.LITTLE architecture, do not use SMP mode since their processors generally cannot run identical instructions from the same copy in memory and they almost always run in AMP mode.
ThreadX/SMP optimizes processor efficiency with automatic load balancing and/or program-directed, thread-processor affinity. Developers can exploit this functionality to run applications virtually without regard to the multiple processors in the system or to explicitly control the use of each processor. ThreadX/SMP automatically runs application threads on any available processor, transparently mapping a multithreaded, real-time system onto a multicore architecture.
In AMP mode, on homogeneous or heterogeneous multicore systems, ThreadX runs on one or more processors, generally from a processor’s local memory, with separate copies for each processor. If the system is made up of heterogeneous processors, then each copy of ThreadX is different, built for operation on a particular processor architecture. For example, TI’s OMAP combines an ARM core and a TI DSP core in a heterogeneous multicore system that could run ThreadX on each processor, or on just one with a different RTOS on the other. Similarly, the new Xilinx Zynq (a two-processor, homogeneous FPGA) could run ThreadX on one processor, while running Linux on the other. Interprocessor coordination is provided by the application using a shared memory mailbox and/or using the PolyCore Software’s MCAPI-compliant Poly-Messenger communications system. This provides the benefits of both operating systems, rather than trying to stretch either one to handle all system functions.
In SMP mode, ThreadX/SMP supports ARM’s MPCore, MIPS’ 34K and 1004K, and Analog Devices’ Blackfin BF561. In AMP mode, ThreadX supports the Xilinx Zynq dual-Cortex-A8 architecture, as well as virtually any heterogeneous architecture.
Shipping and Availability
ThreadX/SMP is available in full source-code form, royalty-free, with project license prices starting at $15,500.
For more information visit Express Logic's Design West Booth 1515, go to this page, call 1-858-613-6640, or e-mail info@expresslogic.com.
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