Product Review
MIPS introduces new Aptiv generation of processor cores
Clive Maxfield5/10/2012 5:47 PM EDT
Comment
Max the Magnificent
This seems a tad uncalled for -- MIPS is an IP company (not a chip company) and ...
jg_
Wow, missing from all the hoopla, is any mention of real silicon, or who the ...
Highlights of this announcement
About the Dhrystone benchmark
Before we plunge into the fray, let's first briefly discuss the benchmarks whose results are quoted throughout this announcement.
We'll start with Dhrystone, which is a synthetic computing benchmark program developed in 1984 by Reinhold P. Weicker. Intended to be representative of system (integer) programming, the Dhrystone grew to become representative of general processor (CPU) performance.
The Dhrystone benchmark contains no floating point operations, thus the name is a pun on the then-popular Whetstone benchmark for floating point operations. The output from the benchmark is the number of Dhrystones per second (the number of iterations of the main code loop per second).
Dhrystone tries to represent the result more meaningfully than MIPS (million instructions per second) because instruction count comparisons between different instruction sets (e.g. RISC vs. CISC) can confound simple comparisons. For example, the same high-level task may require many more instructions on a RISC machine, but might execute faster than a single CISC instruction. Thus, the Dhrystone score counts only the number of program iteration completions per second, allowing individual machines to perform this calculation in a machine-specific way. Another common representation of the Dhrystone benchmark is the DMIPS (Dhrystone MIPS) obtained when the Dhrystone score is divided by 1757 (the number of Dhrystones per second obtained on the VAX 11/780, nominally a 1 MIPS machine ... I LOVE these tidbits of historical trivia).
As the Wikipedia says: "Dhrystone remains remarkably resilient as a simple benchmark, but its continuing value in establishing true performance is questionable."
About the CoreMark benchmark
Now let's briefly introduce the CoreMark benchmark, because this benchmark is core (pun intended) to the announcement from MIPS.
CoreMark is a benchmark released by the non-profit Embedded Microprocessor Benchmark Consortium (EEMBC) that targets the CPU core, similar to Dhrystone. However, CoreMark avoids issues such as the compiler computing the work during compile time; also it uses real algorithms rather than being completely synthetic.
The CoreMark benchmark is generally considered to be better than Dhrystone (with its results in DMIPS) as it mimics a more real-life set of workloads including: data-dependent branches, matrix manipulation, linked lists, integer arithmetic, state-machine operation, and CRC calculations. Also, CoreMark can be easily scaled to run on multi-threaded cores and/or processors containing multiple cores.
Longer pipeline, more complex microarchitectures are challenged for high CoreMark scores (relative to shorter pipeline CPUs) because CoreMark includes a lot of tests/algorithms with complex branching and control flow, and longer pipelines have bigger penalties on branch mispredictions and cache misses. Thus, CoreMark provides an excellent test for a CPU’s branch and L1 cache performance.
Running CoreMark produces a single-number score, allowing users to make quick comparisons between processors (more information is available from www.coremark.org).
Three new processor families from MIPS
And so we come to the announcement itself (sorry for waffling on for so long), which is that MIPS Technologies, a leading provider of industry-standard processor architectures and cores for home entertainment, networking, mobile and embedded applications, has just introduced a new generation of microprocessor cores. The Aptiv Generation cores, including the proAptiv, interAptiv and microAptiv families, offer three distinct performance levels for applications across MIPS’ target segments.
As the folks from MIPS say: "All based on the MIPS32 Release 3 architecture, the products are targeted to build on MIPS’ leadership position in home entertainment, strengthen its position in networking, extend the company’s offering in the high-volume embedded systems segment, and provide a highly-competitive alternative for mobile system development. For mobile devices, the Aptiv Generation offers top-end multicore performance for applications processing in products including tablets and smartphones, efficient multi-threading technology for applications such as baseband processing, and entry-level performance for embedded control and applications such as touchscreen controllers, SIM/security and GPS."
Relationships to existing MIPS families
The following image is intended only to reflect the relative positioning of the new families as compared to current families. For example, the proAptiv family is more powerful that the 1074K and 74K products and addresses the same solution spaces. The existing (classic) MIPS processor families will continue to be available, but users commencing new design projects will almost certainly benefit from migrating to Aptiv generation processors.
proAptiv family key features
With regard to the image above, at the time of this writing, ARM has not publically provided CoreMark results for the Cortex-A15.
Major architectural features and enhancements include:
interAptiv family key features
Major architectural features and enhancements include:
microAptiv family key features
Product specifications and details
For detailed product information including benchmarks, specifications, datasheets and more, visit www.mips.com/aptiv.
Availability
All Aptiv core families can be licensed now. The proAptiv family will be generally available in mid-2012 supporting a range of functional and performance points with single and multi-core versions. The new proAptiv FPU is also available. The interAptiv family will be available in mid-2012 in dual- and quad-core configurations, with optional FPU. Single core versions will be available in the fourth quarter. The microAptiv family is available now, with cache/MMU or non-cached core options. For more information on product availability, contact info@mips.com or visit www.mips.com/aptiv
Footnotes
1The Dhrystone 2.1 and CoreMark 1.0 numbers were achieved using Mentor Sourcery CodeBench v2011.03-94, gcc 4.5.2
2Based on publicly available information from ARM, CoreMark scores from EEMBC CoreMark website, and material available on the Internet
If you found this article to be interest, visit Microcontroller / MCU Designline where – in addition to my blogs on all sorts of "stuff" (also check out my Max's Cool Beans blog) – you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of designing and using microcontrollers.
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
Last but certainly not least, make sure you check out all of the discussions and other information resources at MicrocontrollerCentral.com, including blogs by yours truly.
- A new generation of processor cores offering a high level of performance and efficiency for applications across the home entertainment, networking, mobile and embedded segments
- High-performance proAptiv core achieves the highest CoreMark/MHz score reported for any licensable IP core, together with leading silicon efficiency
- Multi-threaded interAptiv core delivers leading performance efficiency, achieving higher CoreMark/MHz than competing cores in similar die area
- Highly-efficient microAptiv core achieves highest CoreMark/MHz score among microcontroller- class cores; adds DSP acceleration and security
- Several lead licensees already signed for Aptiv cores
About the Dhrystone benchmark
Before we plunge into the fray, let's first briefly discuss the benchmarks whose results are quoted throughout this announcement.
We'll start with Dhrystone, which is a synthetic computing benchmark program developed in 1984 by Reinhold P. Weicker. Intended to be representative of system (integer) programming, the Dhrystone grew to become representative of general processor (CPU) performance.
The Dhrystone benchmark contains no floating point operations, thus the name is a pun on the then-popular Whetstone benchmark for floating point operations. The output from the benchmark is the number of Dhrystones per second (the number of iterations of the main code loop per second).
Dhrystone tries to represent the result more meaningfully than MIPS (million instructions per second) because instruction count comparisons between different instruction sets (e.g. RISC vs. CISC) can confound simple comparisons. For example, the same high-level task may require many more instructions on a RISC machine, but might execute faster than a single CISC instruction. Thus, the Dhrystone score counts only the number of program iteration completions per second, allowing individual machines to perform this calculation in a machine-specific way. Another common representation of the Dhrystone benchmark is the DMIPS (Dhrystone MIPS) obtained when the Dhrystone score is divided by 1757 (the number of Dhrystones per second obtained on the VAX 11/780, nominally a 1 MIPS machine ... I LOVE these tidbits of historical trivia).
As the Wikipedia says: "Dhrystone remains remarkably resilient as a simple benchmark, but its continuing value in establishing true performance is questionable."
About the CoreMark benchmark
Now let's briefly introduce the CoreMark benchmark, because this benchmark is core (pun intended) to the announcement from MIPS.
CoreMark is a benchmark released by the non-profit Embedded Microprocessor Benchmark Consortium (EEMBC) that targets the CPU core, similar to Dhrystone. However, CoreMark avoids issues such as the compiler computing the work during compile time; also it uses real algorithms rather than being completely synthetic.
The CoreMark benchmark is generally considered to be better than Dhrystone (with its results in DMIPS) as it mimics a more real-life set of workloads including: data-dependent branches, matrix manipulation, linked lists, integer arithmetic, state-machine operation, and CRC calculations. Also, CoreMark can be easily scaled to run on multi-threaded cores and/or processors containing multiple cores.
Longer pipeline, more complex microarchitectures are challenged for high CoreMark scores (relative to shorter pipeline CPUs) because CoreMark includes a lot of tests/algorithms with complex branching and control flow, and longer pipelines have bigger penalties on branch mispredictions and cache misses. Thus, CoreMark provides an excellent test for a CPU’s branch and L1 cache performance.
Running CoreMark produces a single-number score, allowing users to make quick comparisons between processors (more information is available from www.coremark.org).
Three new processor families from MIPS
And so we come to the announcement itself (sorry for waffling on for so long), which is that MIPS Technologies, a leading provider of industry-standard processor architectures and cores for home entertainment, networking, mobile and embedded applications, has just introduced a new generation of microprocessor cores. The Aptiv Generation cores, including the proAptiv, interAptiv and microAptiv families, offer three distinct performance levels for applications across MIPS’ target segments.
As the folks from MIPS say: "All based on the MIPS32 Release 3 architecture, the products are targeted to build on MIPS’ leadership position in home entertainment, strengthen its position in networking, extend the company’s offering in the high-volume embedded systems segment, and provide a highly-competitive alternative for mobile system development. For mobile devices, the Aptiv Generation offers top-end multicore performance for applications processing in products including tablets and smartphones, efficient multi-threading technology for applications such as baseband processing, and entry-level performance for embedded control and applications such as touchscreen controllers, SIM/security and GPS."
Relationships to existing MIPS families
The following image is intended only to reflect the relative positioning of the new families as compared to current families. For example, the proAptiv family is more powerful that the 1074K and 74K products and addresses the same solution spaces. The existing (classic) MIPS processor families will continue to be available, but users commencing new design projects will almost certainly benefit from migrating to Aptiv generation processors.
proAptiv family key features
- Leading high-end CPU performance efficiency delivering over 4.4 CoreMark/MHz and
- 3.5 DMIPS/MHz1 in considerably smaller area compared to competing IP cores2
- Ideal for applications processing in connected consumer electronics such as high-end mobile devices and “smart” home entertainment products, and control plane processing in networking applications
- Efficient top-end performance minimizes the need for exotic power management schemes such as “big.LITTLE” in many mobile applications
- 60-75% higher performance on CoreMark and DMIPS scores compared to MIPS32 74K/1074K superscalar single/multicore products
- Highly-scalable solution leveraging up to six cores connected in a multi-core Coherent Processing System (CPS)
With regard to the image above, at the time of this writing, ARM has not publically provided CoreMark results for the Cortex-A15.
Major architectural features and enhancements include:
- High-performance multi-issue, deeply out-of-order (OoO) architecture with state-of-the-art branch prediction
- New higher-performance floating point unit (FPU) with higher synthesizable frequency for 1:1 clock with core and native double-precision execution
- Single-core and multi-core (up to six core) configurations
- Performance-enhanced, tightly-integrated second generation Coherence Manager and L2 cache controller with lower total latency
- MIPS Digital Signal Processing (DSP) Application Specific Extension (ASE) v2
- Enhanced Virtual Address (EVA) for efficient 32-bit address map utilization to reach 3GB+ user space
interAptiv family key features
- The interAptiv core leverages a balanced nine-stage pipeline with multi-threading to deliver leading performance efficiency, achieving greater than 50% more CoreMark/MHz than competing cores in similar die area1,2
- Ideal for highly-parallel applications requiring cost and power optimization, such as smart gateways, baseband processing in LTE user equipment and small cells, SSD controllers and automotive equipment
- Highly-scalable solution leveraging one or more threads per core, and up to four cores connected in a multi-core Coherent Processing System (CPS)
Major architectural features and enhancements include:
- Multi-threaded pipeline implements dual virtual processors, appearing as two complete CPUs to an SMP Linux operating system
- Hardware Quality of Service (QoS), thread management support and inter-thread communication enable optimal control for real-time applications
- Performance-enhanced, tightly-integrated second generation Coherence Manager and L2 cache controller with lower total latency
- Support for up to two I/O coherency units
- Core and CPS-level power management features
- Error Checking and Correction (ECC) support in L1 data cache, L2 cache and data SPRAM
- Enhanced Virtual Address (EVA) for efficient 32-bit address map utilization to reach 3GB+ user space
- Optional floating point unit
microAptiv family key features
- Low-power, compact, real-time embedded processor core with integrated standard I/O interfaces, building on popular MIPS32 M14K core family with microMIPS code compression instruction set architecture
- Integrates DSP and SIMD functionality to address signal processing requirements for a wide range of embedded segments including industrial control, smart meters, automotive and wired/wireless communications
- Leverages highly-efficient 5-stage pipeline to achieve 3.09 CoreMark/MHz and 1.57 DMIPS/MHz1 in microMIPS mode, with 40% and 25% higher performance, respectively, compared to competition2
- MCU and MPU (with integrated cache controller/MMU) product versions available for microcontroller and embedded applications
- Compared to previous generation MIPS cores and competitive cores, offers greater range of design features for both control and DSP operations
- New memory protection unit for enhanced program code and data security, microMIPS-only execution mode, secure debug and 2-wire cJTAG support
Product specifications and details
For detailed product information including benchmarks, specifications, datasheets and more, visit www.mips.com/aptiv.
Availability
All Aptiv core families can be licensed now. The proAptiv family will be generally available in mid-2012 supporting a range of functional and performance points with single and multi-core versions. The new proAptiv FPU is also available. The interAptiv family will be available in mid-2012 in dual- and quad-core configurations, with optional FPU. Single core versions will be available in the fourth quarter. The microAptiv family is available now, with cache/MMU or non-cached core options. For more information on product availability, contact info@mips.com or visit www.mips.com/aptiv
Footnotes
1The Dhrystone 2.1 and CoreMark 1.0 numbers were achieved using Mentor Sourcery CodeBench v2011.03-94, gcc 4.5.2
2Based on publicly available information from ARM, CoreMark scores from EEMBC CoreMark website, and material available on the Internet
If you found this article to be interest, visit Microcontroller / MCU Designline where – in addition to my blogs on all sorts of "stuff" (also check out my Max's Cool Beans blog) – you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of designing and using microcontrollers.
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
Last but certainly not least, make sure you check out all of the discussions and other information resources at MicrocontrollerCentral.com, including blogs by yours truly.
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chrmjenkins
5/11/2012 10:59 AM EDT
While these new cores look impressive, MIPS has a huge hill to climb to even scrape at the level ARM is in the embedded market.
Also, kudos to their marketing team taking a dig at everything ARM touts about Eagle and looking forward. However, I don't think big.LITTLE counts as exotic. It's a pretty intuitive jump given the space's needs. Why spend so much engineering effort making one design fit all needs when you can easily produce two and let the customer decide?
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Mark.Throndson
5/14/2012 5:56 PM EDT
With the proAptiv family, MIPS is providing top performance very efficiently in one CPU core design. This delivers inherent benefits for low power system design. Designers should evaluate whether using simpler DVFS and multi-core clock/voltage gating techniques with an efficient core can meet system power budget goals before expanding to more costly dual architecture schemes such as “big.LITTLE” (more core license fees and more cost per silicon).
That said, if a big.LITTLE type low power scheme is desired, an efficient single core architecture can be used with synthesis/implementation variation within a process node to deliver both high performance and low power core groups within a single coherent multi-core cluster. Because it is the same processor core - just implemented to two extremes - there are no architecture compatibilities to worry about, no performance “divots” during transitions between two different microarchitectures, and a less complex and lower cost implementation due to one shared coherence manager and L2 cache.
As to the question about engineering design costs, if you assume that all design teams are trying to implement a good design, two designs will take a lot more engineering effort than one.
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BJameson
5/15/2012 4:06 PM EDT
The comment on "high performance and lower power core groups within a single coherent multi-core cluster" implies that the cores can be run at different voltages and frequencies at the same time. Is this the case, or is additional customization required by a licensee to enable this? It would seem that enabling the cores to run at different frequencies would require bridges between the cores and the L2 that would increase latency above what is listed in the product description. It sounds like what is being described here are features and specs, some of which are mutually exclusive. Kind of like, "you can have high performance, or power scalability, but not both." Would be good to clarify this point.
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Mark.Throndson
5/16/2012 1:31 AM EDT
My earlier response was not meant to imply cores running at different voltages and frequencies at the same time within a single cluster. I was just trying to keep the answer as concise as possible.
To elaborate a bit further, the core groups would be implemented to different operating points (high performance and low power implementations), but the groups would not be “on” at the same time, with one exception - a common transition frequency that both core groups are capable of operating at. Under those guidelines, there isn’t a need for the coherence interconnect/L2$ to deal with connecting to multiple cores running at different speeds at the same time. You can imagine that with all cores being based on the same microarchitecture and running at the same frequency within one coherent cluster with one L2$, the transition process from low power to high performance core groups (or vice versa) is relatively straightforward.
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jg_
5/18/2012 5:21 AM EDT
Wow, missing from all the hoopla, is any mention of real silicon, or who the early adopters who are sampling devices right now are ?
Availability of real devices is a better milestone. One would almost think they were keen to talk up a stock price ?
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Max the Magnificent
5/18/2012 4:48 PM EDT
This seems a tad uncalled for -- MIPS is an IP company (not a chip company) and as such this announcement is about introducing IP cores, which -- by their very nature -- will take some time to end up in silicon. This announcement is no different to any other IP core launch that MIPS (and their competitors) have done in the past...
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