Modern System-on-Chip (SoC) designs are facing the problem of inaccessibility of important control and bus signals. These signals often lay behind the physical pins of the device, thereby rendering traditional measurement instrumentation useless in many cases.
The best way to get around those limitations, is to use on-chip debug tools for the tasks verification and software debugging. "DoCD from Digital Core Design (DCD) allows hardware breakpoints, trace, variables watch, and multi-C-source debugging,"
explains Jacek Hanke, DCD’s CEO. "Moreover, our Debug Software can work both as a hardware debugger and a software simulator. Some tasks can be validated at software simulation level and – following this step – you can continue real-time debugging, by uploading code into silicon."
The advantage of an on-chip debugger in an integrated environment with a graphical user's interface is improved design productivity. DoCD offers the ability to display/modify memory contents and processor / peripheral register windows, along with information tracing and the ability to see the related C/ASM source code.
The complete DoCD system consists of three major elements as follows:
- Hardware Assisted Debugger: Pendrive packaged, HAD2 is a small hardware adapter that manages communication between the Debug IP Core (JTAG protocol) inside the silicon and a USB port of the host PC, running DoCD Debug Software.
- Debug Software (DS): A Windows-based application that is compatible with all existing compilers and assemblers. The DS was designed to work in two major modes: software simulator and hardware debugger. These modes allow pre-silicon software validation in simulation mode followed by real-time debugging of developed software inside the silicon using the debugger mode. Once loaded, the program may be observed in a Source Window, run at full-speed, single stepped by machine or C-level instructions, or stopped at any of the user-defined breakpoints.
- Debug IP Core: A real-time hardware debugger that provides access to all chip registers, memories, and peripherals connected to the IP Core. It controls CPU work using non-intrusive methods. The Debug IP Core is provided as VHDL or Verilog source code, as well as a CPLD/FPGA EDIF netlist.
Many SoC designs have both power and area limitations. The DoCD debug IP Core can be scaled to control gate count. The benefit is fewer gates, for lower use of power and core size, while maintaining excellent debug abilities. Typically, all of the features are utilized in pre-silicon debug (i.e. hardware debugging or FPGA evaluation) with fewer features implemented in the final silicon.
Table 1. On-chip debugger area/resource utilization.Click here
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