Product Review
DCD's DT8051 powerful, tiny 8-bit CPU
Clive Maxfield11/6/2012 10:47 AM EST
Comment
tomeq
I think that 4000 gates is something which makes the difference. I would agree ...
MCUBob
So, the difference is 4000 gate counts, whatever gate counts are as there are ...
The DT8051 from Digital Core Design (DCD) is an area-optimized tiny soft core of a single chip 8-bit embedded microcontroller, based on the most popular 8051 MCU.
For many applications this IP core offers an excellent solution, especially when you consider that even a stripped-down 32-bit ARM Cortex-M0 requires more than 10000 gates.
"In terms of the cost an area of silicon-proven DT8051, not just other 8-bit MCUs, but also a 32-bit processor licensing comes close," says Tomek Krzyzak, the Vice President of Digital Core Design. "Moreover, our DT8051 can run in very small FPGA devices or can be just a tiny fragment of a Sys-tem-on-Chip ASIC – as the old saying goes: small is beautiful."
A very low gate count and small silicon area allows the core to run at up to 300 MHz using the Hynix 0.18 library (this is equivalent in performance to the original 80C51 being clocked at 2400 MHz).
The DT8051 soft core is 100% binary-compatible with industry-standard 8051 8-bit microcontrollers, but in comparison to its ancestor, DCD’s IP core has a very low gate count architecture, requiring only 6,650 ASIC gates for the complete system with peripherals and the DoCD on-chip debugger.
But small size would not mean anything without appropriate performance. "The DT8051 could be named a 'mighty power,'" says Piotr Kandora, a VP & Director of R&D at DCD. "The Dhrystone 2.1 benchmark program runs exactly 8.1 times faster than the original 80C51 at the same frequency. The performance results are more than 2 times higher than the nearest competitive designs."
The DT8051 includes a 2-wire DoCD on-chip debugger (TTAG), up to eight external interrupt sources, an advanced Power Management Unit, Timers 0&1, I/O bit addressable Ports, full duplex UART and interface for external SFR.
The DT8051 is delivered with fully automated test bench and complete set of tests, allowing easy package validation, at each stage of SoC design flow.
Click Here for more information.
If you found this article to be interest, visit Microcontroller / MCU Designline where – in addition to my Max's Cool Beans blogs on all sorts of "stuff" – you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of designing and using microcontrollers.
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
Last but certainly not least, make sure you check out all of the discussions and other information resources at All Programmable Planet. For example, in addition to blogs by yours truly, microcontroller expert Duane Benson is learning how to use FPGAs to augment (sometimes replace) the MCUs in his robot (and other) projects.
For many applications this IP core offers an excellent solution, especially when you consider that even a stripped-down 32-bit ARM Cortex-M0 requires more than 10000 gates.
"In terms of the cost an area of silicon-proven DT8051, not just other 8-bit MCUs, but also a 32-bit processor licensing comes close," says Tomek Krzyzak, the Vice President of Digital Core Design. "Moreover, our DT8051 can run in very small FPGA devices or can be just a tiny fragment of a Sys-tem-on-Chip ASIC – as the old saying goes: small is beautiful."
A very low gate count and small silicon area allows the core to run at up to 300 MHz using the Hynix 0.18 library (this is equivalent in performance to the original 80C51 being clocked at 2400 MHz).
The DT8051 soft core is 100% binary-compatible with industry-standard 8051 8-bit microcontrollers, but in comparison to its ancestor, DCD’s IP core has a very low gate count architecture, requiring only 6,650 ASIC gates for the complete system with peripherals and the DoCD on-chip debugger.
But small size would not mean anything without appropriate performance. "The DT8051 could be named a 'mighty power,'" says Piotr Kandora, a VP & Director of R&D at DCD. "The Dhrystone 2.1 benchmark program runs exactly 8.1 times faster than the original 80C51 at the same frequency. The performance results are more than 2 times higher than the nearest competitive designs."
The DT8051 includes a 2-wire DoCD on-chip debugger (TTAG), up to eight external interrupt sources, an advanced Power Management Unit, Timers 0&1, I/O bit addressable Ports, full duplex UART and interface for external SFR.
The DT8051 is delivered with fully automated test bench and complete set of tests, allowing easy package validation, at each stage of SoC design flow.
Click Here for more information.
If you found this article to be interest, visit Microcontroller / MCU Designline where – in addition to my Max's Cool Beans blogs on all sorts of "stuff" – you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of designing and using microcontrollers.
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
Last but certainly not least, make sure you check out all of the discussions and other information resources at All Programmable Planet. For example, in addition to blogs by yours truly, microcontroller expert Duane Benson is learning how to use FPGAs to augment (sometimes replace) the MCUs in his robot (and other) projects.
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MCUBob
11/6/2012 2:30 PM EST
So, the difference is 4000 gate counts, whatever gate counts are as there are several ways to count them.
If a company doesn't have a license for the Cortex-M0(+) it can be interesting indeed. On the other hand, the silicon size difference in a .18 um process is just about 0.1 mm2, sometimes this fraction of a cent lower cost might make a difference. However, possibilities with an ARM core are endless and many companies have been using ARM M-cores for a few years and probably don't want to head this step back.
Some data is missing in this article; what is the power consumption of this core? If it can beat the M0+, the lowest power MSP430s, PICs or AVRs that can make a difference. If not, I doubt this core will fly just because it offers the lowest advertised gate count. Power, licensing costs and support for the propriety debugging interface are not covered in this article.
The additional information on the DCD webpage shows support from all the known 51 compiler vendors as expected for a binary compatible core. It also shows the propriety debugger interface that depends on the also propriety hardware DCD hardware assisted debugger.
All this propriety stuff for what they claim a standard core?
Been there and done that, using an almost standard 51. Won't do it again.
Robert
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tomeq
11/7/2012 2:37 AM EST
I think that 4000 gates is something which makes the difference. I would agree that 400 or 40 gates could be statistic error, but 4k, especially in 8051 could be useful.
When someone's licensing ARM, he surely gonna stick to that. But what about thousands or millions of designs based on 8051? Wouldn't be interesting replace good, old fashion 8051 with DT8051 which consumes less energy, less area and gives 8x higher performance. When you drive to job, you don't need a Ferrrari car - speed limits and traffic jams will kill the joy of driving that dream from Maranello.
And re the proprietary stuff which is being offered with DT8051. As it is 100% compatible with 8051 standard, you can use all the tools you have for 51. And if DCD offers extra, proprietary tools, which can boost your design - I can only say: gimme more.
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