Protocol analyzer performs DDR4 and JEDEC timing analysis

LeCroy Corporation’s new validation platform provides DDR4 bus and JEDEC timing analysis.  The Kibra 480 platform features proprietary probing technology designed for non-intrusive monitoring of DDR4's higher transfer speeds without signal calibration and setup.  The system analyzes bus traffic while identifying timing violations and displays both commands and errors using a full function waveform viewer. LeCroy claims that with support for testing both DDR3 and DDR4, the system allows designers to speed memory integration and ensure design manufacturability.

The Kibra 480 trigger logic identifies over 65 JEDEC timing and command violations across all ranks and banks simultaneously. This overcomes limitations with logic analyzer-based solutions using state-based triggering that tracks only two or three violations simultaneously.  In addition, the Kibra 480 highlights errors in the timing display so users see and verify interoperability and compliance to the DDR4 specification.

The Kibra system software provides a  Bank State View to examine distribution of I/O operations across all banks. Additionally, the ability to capture serial presence detect (SPD) data lets developers automatically discover the memory parameters used by the system under test. The Kibra 480, compatible with DDR3, can be extended to address the next generation DDR4 standard by using different interposer probes.

Customers can purchase the system with interposer probe sets for DDR3, DDR4 or both.  The LeCroy Kibra 480 will be available in the 2nd quarter of 2012.

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