Deal helps high-performance computing designers leverage the power of an FPGA

Combination of Starbridge Design Software and Nallatech Hardware Delivers Scalable, Flexible, Affordable FPGA-Based Systems

Salt Lake City, Utah and Baltimore, Md.—Taking the lead in addressing strategic markets for field programmable gate array (FPGA) systems, Starbridge Systems and Nallatech today announced a worldwide strategic partnership that offers a unique combination of software, hardware and services suited for high-performance computing applications. These combined offerings make the power of FPGAs accessible to system engineers involved in high-performance computing applications in markets such as defense and military, homeland security and bioinformatics.

The agreement follows the porting of Starbridge Systems Viva FPGA development software to Nallatech’s reconfigurable computer systems. This combination provides ease of algorithm development on a wide range of FPGA platforms—from inexpensive low gate-count boards to powerful high-end multi-FPGA architectures.

“This strategic alliance is truly a case of taking the best elements of two companies to establish a powerful, scalable and affordable computing system for demanding applications,” said Allan Cantle, CEO of Nallatech. “Starbridge’s Viva provides a powerful and easy-to-use front end tool for Nallatech’s FPGA-based hardware systems.”

“Offering Viva with Nallatech’s scalable, modular hardware platform extends the benefits of Starbridge’s expertise in Hypercomputing to a much broader range of users,” said Kurt Dobson, CEO of Starbridge Systems. “The Nallatech/Starbridge relationship makes high-performance reconfigurable computing accessible to the entry level user as well as the power user.”

With Starbridge’s Viva, a fully integrated, object oriented, graphical development environment, developers can create efficient custom circuitry for running complex algorithms directly in the FPGA hardware of Nallatech’s reconfigurable computer systems. Viva algorithms can be tuned for maximum performance (by using more hardware), smallest physical size (by using very few gates), or anything in between.