QuickLogic introduces low power PolarPro FPGAs

Quicklogic Corporation has announced a new family of FPGA devices known as PolarPro. The PolarPro family boasts a number of innovative architectural features, including an inactive power consumption of only 10uA and special embedded first-in, first-out (FIFO) controller blocks.

Very low power (VLP) mode
One extremely important feature of the new PolarPro devices is a very low power (VLP) mode. This mode is controlled by a single VLP pin, which can be driven by an external device such as a general-purpose microprocessor or a specialized mobile application processor. When placed in its VLP mode, the PolarPro draws under 10uA, which is less than 1/1,000 and 1/10,000 that of Flash-based and SRAM-based FPGAs, respectively (Fig 1).

1. In VLP mode, the PolarPro draws less than 10uA.

One key aspect of the PolarPro's VLP mode is the retention of any internal register values and also any values on the I/Os. Another important feature is "instant-on" with full operation when the device is brought out of its VLP mode.

There are a number of applications in which the PoLarPro's VLP mode is of extreme interest. For example, consider a portable media player containing a mobile application processor and a hard disc drive (HDD). In such a case, a CPLD or FPGA is often used as the HDD controller. However, the HDD will be active only approximately 0.2 percent of the time when playing 128 kbps MP3 audio and only approximately 5.2 percent of the time when playing MPEG4 video.

As shown in the above figure, traditional CPLDs and FPGAs connected to the mobile application processor bus will continue to draw power, even when the HDD is inactive and they have no throughput (payload). By comparison, using a PolarPro-based FPGA controller eliminates excess inactive power consumption.

The result is a dramatic increase in battery life for mobile, handheld applications. In the case of one example media player design, the video playback time was extended from 2.5 hours (without PolarPro) to 10.8 hours (with a PolarPro-based solution). In another media player example, the video playback time was increased from 5 hours to 14.5 hours.

Embedded first-in, first-out (FIFO) controller blocks
When programmable logic is used in systems with a processor, wired or wireless connectivity, and potentially non-volatile storage such as miniature hard disks and memory sticks, the logic often must bridge different clock frequency domains.

One very common technique for addressing this is to use blocks of embedded RAM in the FPGA to implement FIFOs. However, this requires the designer to utilize and configure valuable logic resources in the FPGA. Also, creating a FIFO with "almost full" and "almost empty" flags coupled with asynchronous operation in which the input and output ports of the FIFO are clocked at completely different frequencies is a non-trivial task that will consume valuable engineering time and resources that could be better spent on creating the differentiating portion of the design.

In order to address this issue, PolarPro devices feature built-in FIFO controllers and other specialized circuitry. This provides a seamless, cost-effective way to bridge several clock domains together, allowing designers to focus on other important energy conserving strategies.

By means of a simple step-by-step Wizard in the QuickWorks design software supplied by QuickLogic, designers can quickly and easily generate the RTL wrappers and testbenches that enable the PolarPro embedded FIFO blocks to operate in a given design. These RTL wrapper files can be instantiated in the top level FPGA design and will automatically configure the embedded FIFO and RAM blocks in the PolarPro device during the FPGA place-and-route stage. Key features of the PolarPro FIFOs are as follows:

• Asynchronous input and output ports (these ports can be clocked at completely different frequencies).
• Almost empty and almost full output flags.
• Level indicator flag vectors for both the input and output side of the FIFO.
• Data flush inputs for both the input and output side of the FIFO.
• For FIFOs utilizing one RAM block, programmable aspect ratios of 256x18 or 512x9 are independently configurable on the input and output ports.
• For FIFOs utilizing two RAM blocks, programmable aspect ratios of 256x36, 512x18, or 1024x9 are independently configurable on the input and output ports.

Integrating FIFO controllers into the PolarPro architecture as hard IP reduces the effective silicon area required to implement such functions by 97%, thereby significantly reducing power consumption, freeing up programmable logic resources for other tasks, and delivering guaranteed asynchronous FIFOs for pennies.

Pricing and availability
Version 9.8 of QuickWorks will be available for download from the QuickLogic website in early December. It will include timing, area and power-optimized designs for the PolarPro family suite of FPGA development tools.

The 640 logic cell device, the QL1P100, will be sampling in December, with the other members of the family expected to sample during 2006. In high volumes, the QL1P100 will be priced as low as $2.95.

More information is available at www.quicklogic.com.