Altera unveils 65 nm Stratix III FPGA families and design tools

Things have changed. Today's high-end FPGAs can easily account for 40% or more of the system's power budget, which means that any savings can be extremely significant. This is one of the reasons why the folks at Altera have made power a key consideration in their newly announced 65 nm Stratix III FPGA families.

In fact, Stratix III devices address the "4Ps" of customer requirements: Power, Performance, Productivity, and Price. The migration to the 65 nm technology node dramatically increases density and performance while reducing price per logic element. Also, all copper routing coupled with the use of strained silicon, low-K dielectric, and a super-thin gate oxide layer provide increased performance; while multi-threshold transistors, variable gate-length transistors, and triple gate oxide provide reduced power.

Coupled with other power-saving techniques (discussed below), the result is that Stratix III devices deliver 50% lower power, 25% higher performance and 2× the density compared to their previous generation Stratix II counterparts.

Application-domain optimized solutions
In order to meet diverse application needs, Stratix III devices are offered in three major variants: the Strattix III L (Logic), Stratix III E (Enhanced), and Stratix III GX (Transceivers).

• Stratix III L FPGAs deliver balanced logic, memory and DSP resources for general-purpose applications.
• Stratix III E FPGAs provide enhanced memory and DSP resources for memory- and DSP-intensive applications.
• Stratix III GX FPGAs offer integrated transceivers for high-bandwidth interface applications.

1. Stratix III devices are offered in three major variants.

The logic-rich L family includes six members spanning the EP3SL50, with 50K equivalent logic elements (LEs), up to the industry's largest FPGA, the EP3SL340 with 340K equivalent LEs.

The memory- and DSP-rich E family includes four family members spanning the EP3SE50, with 50K equivalent LEs, up to the EP3SE260, with 260K equivalent LEs. This family includes the EP3SE110 with 896 18x18 multipliers for the highest performance programmable DSP available. Vertical migration between the L and E families is fully supported so customers can support one board and system design across various performance and feature price points. This is particularly useful in wireless and wireline systems, because it allows multiple price points and multiple channel densities to be supported with a single board and system design.

Table 1. Summary of the Stratix III device family members.
(Click this image to view a larger, more detailed version)

Altera say that details pertaining to the transceiver family will be announced at a future date.

Two major power-centric architectural innovations
Stratix III FPGAs boast two new technologies that dramatically lower power while meeting high-performance requirements. First is the ability to select the core voltage. That is, as opposed to providing only a single core voltage of 1.0V, designers can choose to set the core voltage of these devices to either 1.1V for designs needing the highest performance or 0.9V for designs requiring minimum power consumption (Table 2).

Table 2. Stratix III devices boast selectable core voltage.

But the really clever architectural feature is Altera's innovative Programmable Power Technology, which maximizes performance where needed while delivering the lowest power elsewhere in the design. Programmable Power Technology enables every programmable logic array block (LAB), DSP block, and memory block to independently operate at high-speed or low-power mode (Fig 2).

2. Programmable power technology
(Speed where you need it, low power where you don't)

Any element that are in the critical path and demand the highest performance can be set into their high-speed mode, while all of the other elements can be put into their low-power mode.

The HardCopy cost-reduction path
In the case of high-volume applications, there is a seamless migration path from Stratix III FPGA designs into Altera's HardCopy Structured ASICs, which offer lower cost, lower power consumption, and higher performance (Fig 3).

3. Migrating to HardCopy Structured ASICs for high-volume applications.

State-of-the-art security and IP protection
In today's government agencies, military, and highly competitive commercial environments, design security is an important consideration for digital designers requiring a very high level of protection for their designs.

Stratix III devices are the industry's first FPGAs to support configuration bitstream encryption using the Advanced Encryption Standard (AES) algorithm with 256-bit key. Selected by the National Institute of Standards and Technology (NIST) and adopted by the U.S. government to protect sensitive information, AES is the most advanced encryption algorithm available today.

Furthermore, other FPGA vendors only support encryption using a battery to power up or back up a volatile key. By comparison, Stratix III FPGAs allow designers to choose between the flexibility of a battery backed-up volatile key or the ultimate security of a non-volatile scrambled key.