has announced a collaboration with the industry's leading EDA companies to address the challenges of ultra-high capacity FPGA design verification.
Xilinx engineers will be joined by Cadence, Mentor, and Synopsys to define and implement new verification flows to maximize productivity and quality of results for ultra high-density designs targeting today's 65 nm FPGAs as well as new and emerging FPGA architectures.
The collaboration will focus on expanding coverage, improving simulation runtime, and reducing verification time in an environment that allows designers to achieve aggressive design goals. Major releases of these tools and methodologies are expected in the first half of 2008.
"With the growing complexity of today's 65 nm FPGAs, verification has become a major time consuming portion of the FPGA design flow," said Bruce Talley, vice president of the Design Software Division at Xilinx. "By collaborating with the industry's leading EDA providers, we can develop solutions to address the challenges faced by our customers at 65 nm and beyond."
Xilinx introduced the industry's first 65 nm FPGAs. Shipping since May of 2006, the Virtex-5 FPGA platform includes devices with up to 330,000 logic cells, 10 Mb on-chip memory, 1,200 I/Os, and a host of additional hardened intellectual property (IP) blocks. Ongoing growth trends in FPGA architecture present escalating challenges for logic designers with increasing density points and capabilities across a wide range of application domains. The companies will work together to build upon existing technologies to develop next-generation verification solutions, enabling system designers to streamline the verification process.
"Joining with Xilinx in this effort helps ensure we are creating verification technology needed for today's complex devices," said Mitch Weaver, corporate vice president and general manager for Advanced Verification Systems at Cadence Design Systems, Inc. "Leveraging Cadence's proven leadership in simulation and functional verification, we can bring proven technology and methods to the ultra-high capacity FPGA user community."
"Today, FPGA verification flows rival advanced verification flows for complex ASICs and SoCs," said Robert Hum, vice president and general manager of Mentor Graphics Design Verification and Test division. "A focused effort on verification will bring the latest technology such as assertions, transaction-level modeling, clock domain crossing, formal verification and others to the FPGA designer."
"Synopsys is committed to delivering verification solutions that provide high performance and quality of results," said Manoj Gandhi, senior vice president and general manager, Verification Group, Synopsys. "By participating in the ultra high-capacity verification collaboration with Xilinx, we are able to align our efforts to bring innovations to market quickly for our mutual customers."