has chosen Altera's
Stratix II FPGAs for its new Series I MAP reconfigurable processor
module used in high-performance computing applications such as financial, defense, energy and biometrics. Systems built with the Series I MAP are part of the SRC-7 product line that can accelerate applications such as Black-Scholes or medical imaging
by over 30 times compared to current dual-core
The Series I MAP is a high-performance compute processor module used to off-load the system processor of compute-intensive applications. It uses the system memory bus to communicate to and from the system processor. The memory bus interface is a cost-effective, low-latency, high-throughput interface ideal for fast data transfer to and from the system processor. The Series I MAP processor plugs into a computer memory slot providing the user with a high-performance, direct-execution logic processor providing millions of gates of user logic, autonomous control functions to minimize overhead effects, high on-board memory bandwidth and high-speed interconnects to the system as well as other MAPs.
Altera is further collaborating with SRC by providing them with a floating-point (FP) compiler enabling accelerated performance and higher logic utilization for their SRC-7 product line. The entire SRC-7 product line maximizes performance by using Altera Stratix II FPGAs. The collaboration provides SRC with a FP compiler for their high-performance systems. For those applications with FP data types, it is claimed that performance can be increased by up to 33 percent compared to existing place and route tools.
Using the FP compiler results in more efficient routing with up to 50 percent less logic required and significant power savings from the logic reduction. The FP compiler enables a Stratix II FPGA to deliver in excess of 20 sustained double precision GFLOPS for fast Fourier transform (FFT) or matrix math applications.
See also Part 2 of the Programmable Logic DesignLine mini-series: FPGA-based hardware acceleration of C/C++ based applications.