Lattice delivers QDR II/II+ memory controller support

The LatticeSC and LatticeSCM FPGA families (collectively referred to as the "LatticeSC/M" family) now support QDRII/II+ rates up to 750Mbps.

The high-speed QDR II and QDR II+ memory controller IP (intellectual property) is implemented in Lattice's unique and low power Masked Array for Cost Optimization (MACO) structured ASIC technology.

The Quad Data Rate II+ memory devices are the latest members of the QDR SRAM memory family and allow data rates above 250 MHz. These new SRAMs are ideal for high-bandwidth, low latency applications. The read and write ports run independently and allow designers to maximize bandwidth without having to worry about the bus contention issues that are typical with other memory devices.

The high bandwidth and low latency characteristics of the QDR II+ memories make them ideal for high-bandwidth applications in which they serve as the main memory for look-up tables, linked lists and controller buffer memory. These are used extensively in next generation switch and router platforms.

Lattice's MACO embedded structured ASIC blocks are available on LatticeSCM FPGA devices and deliver pre-engineered, standard-compliant IP functions developed by Lattice to shorten end-system time to market. Unlike the soft IP cores commonly used with FPGAs, the MACO IP functions are embedded into the devices and there is no distinct IP license fee associated with their use. These enhanced memory controllers provide programmable memory interfaces supporting next generation QDR II and QDR II+ memory devices, as well as DDR I/II and RLDRAM I/II memory devices.

Lattice's ispLEVER version 7.0 software design tool suite supports a complete HDL-based design and verification flow for LatticeSCM devices, as well as other Lattice programmable device families.