Lattice shipping entire 90 nm LatticeECP2M FPGA family

The folks at Lattice Semiconductor say that all five of their LatticeECP2M FPGA devices – ranging in density from 20K LUTS to 95K LUTS – have been qualified and released to volume production.

Originally announced in late 2006 and developed on advanced 90 nm CMOS technology utilizing 300 mm wafers, the LatticeECP2M are low-cost devices that offer high-speed embedded SERDES I/O, plus a pre-engineered Physical Coding Sublayer (PCS) block.

In the not-so-distant past, high-speed embedded SERDES serial I/O with speeds over 3 Gbps was available only on relatively expensive high-end FPGAs. Integrating this capability into a low cost FPGA fabric made this higher performance interface technology accessible to a much broader range of applications in rapidly emerging, cost-conscious markets such as high volume communications, consumer, automotive, video and industrial equipment.

The LatticeECP2M devices also have increased on-chip memory capacity to support higher bandwidth, SERDES-based applications. LatticeECP2M Embedded Block RAM capacity ranges from 1.2 Mbits up to 5.3 Mbits.

The LatticeECP2M FPGA family offers a comprehensive array of features that includes 375 MHz block level performance, 18×18 multipliers, embedded memory, pre-engineered 533 Mbps DDR2 memory interface support, high throughput SPI4.2 support, configuration bitstream encryption, and dual-boot configuration support.

With the addition of 4 to 16 channels of 3.125 Gbps SERDES, the LatticeECP2M FPGAs satisfy the requirements of a broad range of customers who require low cost SERDES capability for PCI Express and Ethernet-based chip-to-chip and small form factor backplane applications.

Cost-optimized SERDES architecture
The SERDES integrated into the LatticeECP2M family has been engineered specifically for implementation in a cost effective, power efficient (power consumption as low as 100 mW) quad-based architecture with 1 to 4 quads, depending on the size of the device.

Each quad features 4 SERDES channels (4 complete TX and RX channels) and supports data rates from 270 Mbps to 3.125 Gbps. A flexible PCS layer that includes 8b/10b encoding, an Ethernet link state machine and rate matching circuitry also are built onto the chip. The SERDES/PCS combination is designed to support today's most common packet-based protocols, including PCI Express, Gigabit Ethernet, Serial RapidIO and wireless interface standards (OBSAI and CPRI).

The combination of SERDES, high performance DSP and a low cost FPGA fabric is extremely attractive to Edge and Access system vendors that are integrating these serial protocols into their wireless base stations, radio network controllers, DSLAMs and other last mile aggregation equipment that enable "triple play" technologies. Mass storage, high-speed server, medical imaging and industrial equipment system designers interested in low cost signal processing also will benefit from the LatticeECP2M family's unique combination of features.

Design tools and intellectual property support
Design support for the LatticeECP2M devices is provided by the latest version of Lattice's ispLEVER design tool suite, Version 7.0 with Service Pack 1. The ispLEVER design tools provide access, in one software package, to all Lattice digital devices and include simulation and synthesis support from Mentor Graphics and Synplicity.

Customers also have easy access to a wealth of Intellectual Property (IP) modules through the IPexpress design flow. IPexpress-supported functions include PCI Express, SGMII, DDR1 and DDR2 memory controllers, and SPI4.2.