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SystemVerilog gets boost from OVM
GABE MORETTI1/10/2008 8:38 AM EST
The OVM, based on IEEE Std. 1800
Distributed under the standard open-source ApacheTM 2.0 license, the OVM source code, documentation and use examples may be downloaded free of charge from www.ovmworld.org . The OVM Web site is the central point of access for the OVM source code, providing information about partners, events, seminars, training, how-to instructions and future plans.
The OVM includes the foundation-level utilities necessary for building advanced object-oriented, coverage-driven verification environments and reusable verification IP (VIP) in SystemVerilog. The OVM reduces the complexity of adopting SystemVerilog by embedding verification practices into its methodology and library, and significantly shortens the time to create verification environments. It easily integrates plug-and-play VIP and ensures code portability and reuse.
Additional functionality is planned for release later in 2008. Cadence and Mentor have
collaborated to ensure that the OVM runs on their simulators and enables backwards compatibility with their existing environments, Advanced Verification Methodology from Mentor Graphics, and Incisive(r) Plan-to-Closure Methodology (Universal Reuse Methodology module) from Cadence.
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