Xilinx EDK delivers processing peripheral IP cores at no additional cost

The 10/100 Ethernet MAC Lite, single precision floating-point unit, industry standard UART (Universal Asynchronous Receiver/Transmitter) 16450/16550 controller and IIC (Inter-Integrated Circuit) interface IP cores can now be licensed at no charge.

Made available through the Xilinx Embedded Development Kit (EDK), the four IP cores have been ported to the enhanced on-chip CoreConnect bus structure, the Processor Local Bus version 4.6 (PLB46) that Xilinx introduced last November, to be implemented in designs using the MicroBlaze soft processor and the PowerPC processor embedded in the Virtex family of FPGAs.

The EDK now includes over 40 popular cores for licensing at no charge that can be used for a wide range of applications for PowerPC and MicroBlaze processor systems. Using the EDK suite of no-fee IP cores, designers can select and build an unlimited number of configurations to meet their needs and not incur the additional costs associated with traditional IP license agreements.

In addition to the no-fee IP cores, numerous other value-core options are available separately from Xilinx and partners including a Tri-Mode Ethernet MAC, USB2, CAN (Controller Area Network), and the FlexRay(TM) controller.

New no-charge peripherals

The IIC interface IP core provides an industry standard two wire, peer-to-peer serial bus interface for device communication. This core provides master, slave, and multi-master operations, supporting 400 KHz fast mode and 100 KHz standard mode. The UART 16450/16550 IP core works in both 16450 and 16550 modes and performs the parallel to serial conversion on characters received from a CPU and serial to parallel conversion on characters received from a microprocessor peripheral.

Optimized to provide the basic Ethernet functions with the least resources used, the 10/100 Ethernet MAC Lite supports IEEE 802.3 Media Independent Interface (MII) to industry standard Physical Layer (PHY) devices and communicates to a processor via a Processor Local Bus (PLB46) interface. This core provides interfaces for both 10 Mbps and 100 Mbps.

The MicroBlaze soft processor has an optional configuration for implementing floating-point support via the automated Platform Studio tool suite. By comparison, the Xilinx auxiliary processor unit (APU) floating-point unit IP core is designed specifically for the PowerPC 405 hard processor core implemented in the Virtex-4 FX family of FPGAs. This core provides support for IEEE 754 floating-point arithmetic operations in single precision. Software applications can use native PowerPC processor floating-point instructions to achieve sustained performance of up to 100 MFLOPS (million floating-point operations per second.)

Availability and pricing
The no-fee IP cores are available now, delivered with the Xilinx EDK and licensed via the online IP registration center. EDK version 9.2 is available for US$495, and includes the MicroBlaze v7 processor core with new optional memory management unit (MMU), Xilinx Platform Studio (XPS) 9.2 tool suite, software drivers, documentation, and reference design examples.

XPS 9.2 supports MicroBlaze and PowerPC processing design for Virtex-5, Virtex-4, Virtex-II Pro, and Spartan-3 FGPAs. XPS 9.2 supports a broad range of computing platforms, including Windows XP (32-bit SP1 & 2), Linux Red Hat Enterprise (32-bit 5.0 & 4.0, 64-bit 5.0) as well as Solaris 9 (2.9/5.9). For more information, please visit www.xilinx.com/processors.