Those busy folks at Xilinx
have announced the availability of a free hardware-verified reference design and associated third-party IP
for the optical internetworking forum
(OIF) SERDES framer interface
level 5 (SFI-5) standard.
The SFI-5 interface enables communication between the optical transmission devices and the network processing system. Based on its 65 nm Xilinx Virtex-5 LX330T FPGAs, the reference design accelerates the development of wired networking systems requiring 40 Gbps payload rates, enabling applications using transport interfaces like OC768/STM256 and OTN OTU-3 in systems such as optical cross connects, fiber optics terminators and repeaters, 40G multiplexers, and test equipment.
The reference design has been hardware verified on the Xilinx ML525 evaluation platform and characterized for skew, temperature, process, and voltage variations to ensure reliable interface, compatible with the OIF SFI-5 standard. Leveraging what Xilinx claims to be the industry's lowest power transceivers – typically consuming less than 100mW per transmitter/receiver pair–" this Virtex-5 LXT FPGA-based reference design uses 17 transceivers (16 for data and one for calibration).
Wired networking designers seeking additional Virtex-5 LXT FPGA solutions for 40G system design can also benefit from IP offerings from Xilinx Alliance program participant Avalon Microelectronics for 40 Gbps applications, including:SxI-5-compliant SFI-5 physical layer core, 40G SONET-768/SDH-256 core with POS and 43G OTU-3 with G.709 FEC or other Enhanced FEC (Click Here for more information).
Pricing and availability
The free reference design for SFI-5 interface is available for download at www.xilinx.com/spi_sfi. The Virtex-5 LX330T FPGA is available today and the ML525 development board will be available in May 2008. For more device information visit www.xilinx.com/virtex5.