The folks at Lattice Semiconductor
tell me that their low-cost LatticeECP2M FPGAs will be on display at the upcoming NAB (National Association of Broadcasters) Show in Las Vegas, April 14-16.
The device's capabilities will be demonstrated at the Sonifex booth, where it has been designed into the RM-HD1 HD-SDI Expansion card for the RM-2S4, RM-2S10 and RM-4C8 line of Reference Monitors. The on-chip SERDES capability and other programmable features of the LatticeECP2M FPGA are used to de-embed audio from an SDI source (SD/HD) and to reclock the SD data on the transmit side (Click Here for more information).
Sonifex chose the LatticeECP2M device for the Reference Monitor products for several reasons. According to Paul Schofield, Director of New Products at Sonifex, "The LatticeECP2M device has a small footprint and can handle both High Definition and Standard Definition digital video signals through the same integrated SERDES. It's a relatively low cost device and the programming tools supplied are fully integrated and well supported. The R&D team at Sonifex is getting some great results from the LatticeECP2M FPGA, so it's definitely been a good choice."
Attendees are encouraged to stop by the Sonifex booth (N4919) to see the demo and register for a free chance to win an iPOD.
Click Here to learn more about the Lattice HD/SD-SDI solution.
About LatticeECP2M FPGAs
The folks at Lattice say that their LatticeECP2M FPGAs are an innovative response to the broad range of customers who have been clamoring for low-cost SERDES capability for chip-to-chip and small form-factor backplane applications.
The LatticeECP2M family maintains all of the compelling features of the 90nm LatticeECP2 family that are required for high-volume, cost-sensitive applications, while dramatically increasing memory capacity (ranging from 1.2 Mbits to 5.3 Mbits), DSP resources (ranging from 24 to 168 multipliers) and adding up to 16 channels of 3.125Gbps SERDES on-chip.
The five devices in the series, ranging in size from 19K to 95K lookup tables (LUTs), provide an inexpensive alternative for implementing PCI Express, Ethernet, Serial RapidIO and CPRI/OBSAI interfaces. A flexible PCS layer that includes 8b/10b encoding, an Ethernet link state machine and rate matching circuitry also are built onto the chip. The SERDES/PCS combination is designed to support today's most common packet-based protocols, including PCI Express, Gigabit Ethernet, Serial RapidIO and wireless interface standards (OBSAI and CPRI).