The folks at Lattice Semiconductor
have announced the successful interoperation of their LatticeECP2M FPGA family with the Linear Technology LTC2274, 16-bit, 105 Msps, high-speed ADC (Analog to Digital Converter) in support of the JESD204 high-speed serial
specification from the JEDEC group. This capability has been demonstrated utilizing standard evaluation boards from both companies.
This standard allows front-end data acquisition to reap the benefits of a low overhead, high-speed serial link to support pure data transport. By working together with Linear Technology, the folks at Lattice were able to demonstrate how this interface dovetails with the integrated, high-speed SERDES channels offered on the LatticeECP2M family of FPGAs.
The end result is that designers can now realize a lower cost, lower power, and smaller footprint solution for the interface between data converters and FPGA devices. This is particularly important for cost sensitive, high volume applications like wireless base stations, which can benefit from the low pin count and high bandwidth that JESD204 brings to the ADC landscape.
With devices starting at a price of less than $10.00 in high volume, the folks at Lattice say that their LatticeECP2M FPGAs provide the lowest cost SERDES-capable FPGAs available, and provide uniquely cost-effective solutions for designs using JESD204/high- speed ADC devices.
Lattice also offers a development board that enables customers to quickly develop a JESD204 receiver using the LatticeECP2M SERDES block. The incoming data can then be processed using the LatticeECP2M fabric and high-speed sysDSP blocks. A reference design can also be provided to allow interoperation with the LTC2274. Click Here for more information.