Lattice announces automotive versions of flash-based non-volatile FPGAs

The folks at Lattice Semiconductor have announced that automotive versions of their non-volatile 90nm Flash-based LatticeXP2 FPGAs (Field Programmable Gate Array) have been characterized and qualified to meet the certification requirements of the AEC-Q100 standard as defined by the Automotive Electronics Council (AEC).

Designated the LA ("Lattice Automotive")-LatticeXP2 family, these production released devices join Lattice's four previously announced automotive LA versions of the MachXO Crossover Programmable Logic Devices, ispPAC-POWR1014/A Programmable Power Manager Devices, ispMACH 4000V and ispMACH 4000Z CPLDs. Production quantities of the new LA-LatticeXP2 devices will be available by the fourth quarter of 2008, and Lattice can provide standard PPAP (Production Part Approval Process) documentation now to automotive customers who require it.

About LA-LatticeXP2 devices
The LA-LatticeXP2 automotive FPGA family includes three members, with capacities from 5K to 17K 4-input Look Up Tables (LUTs). Embedded Block RAM is provided with up to 276 Kbits on-chip in 18 Kbit dual-port blocks. For small scratch pad memories, LUTs also can be converted into small, distributed memory blocks. To support increasingly common DSP applications, up to 5 sysDSP blocks provide hardwired, high-performance pipelined multiply and accumulate functions. The devices have up to four Phase Locked Loops (PLLs) that allow designers to align and synthesize clocks as required in their designs.

Recognizing that power consumption is a critical concern for system designers, Lattice designed the LA-LatticeXP2 family to use a 1.2-volt core voltage for low power consumption. I/O capacities for the family range from 86 to 358 pins. Flexible I/O buffers support the most popular I/O standards, including LVCMOS, SSTL, HSTL and LVDS. These buffers are supported by pre-engineered I/O logic that simplifies the implementation of Double Data Rate (DDR) and source synchronous standards. This combination provides support for DDR2 memory interfaces at 400Mbps, high performance ADC/DACs at up to 750Mbps and 7:1 LVDS display interfaces at above 600Mbps. LA-LatticeXP2 devices are available in thin Fine Pitch Ball Grid Array (ftBGA) packages as well as popular TQFP and PQFP options.

flexiFLASH architecture enables enhanced non-volatile single chip solution
Flash memory blocks are embedded within LA-LatticeXP2 FPGAs to store the device configuration, providing a true single chip solution that Lattice calls the flexiFLASH architecture. At power up or on user command, the data stored in the Flash memory is transferred into SRAM cells that control the configuration of the device. This transfer is done in a massively parallel fashion, enabling the device logic to be available in approximately 1 mS, well ahead of the other devices in the system and much faster than SRAM-based FPGAs that use external boot PROMs, regardless of whether they are provisioned separately on-board or stacked in the same package. This instant-on capability is critical for many system functions such as power up sequencing, address decoding and reset logic.

By keeping the configuration data on-chip, the LA-LatticeXP2 devices also are claimed to be inherently more secure than alternative multiple device or multi-chip module solutions. This security is enhanced by configuration read-back protection modes. A 64-bit erase/program lock protects against accidental or unauthorized device programming. A one time programmable (OTP) mode is provided for ultimate protection against unauthorized programming. Optional 128-bit AES encryption can be used to secure programming data being passed into the device.

The devices also support up to 276 Kbits of FlashBAK memory. This exclusive capability allows Embedded Block RAMs to be initialized at power up from Flash memory. During device operation, designers also can choose to write updated data from the block RAM back into the Flash memory. This provides a method to store data such as Power On Self Test (POST), microprocessor code and calibration data. An additional 0.6 to 2.2 Kbits of Flash memory is provided in the form of Serial TAG memory for general-purpose use by system designers for storage of device revision data, board identifiers and other data.

Availability and pricing
Samples of the LA-LatticeXP2 family 5K and 8K LUT devices in 144 TQFP and 256ftBGA, and of the 17K LUT device in the 256ftBGA package, are available now, with 208-PQFP package options available in the third quarter of 2008. The LA-LatticeXP2-5 in the 144 TQFP package will be priced as low as $4.50 in 100,000 unit quantities for delivery in the first half of 2009.