Lattice announces Service Pack 1 for ispLEVER 7.1 FPGA design tool suite

This release integrates Lattice's ORCAstra configuration design utility, features Reveal Logic Analyzer support on the Linux Operating System, adds new versions of Synopsys' Synplify Pro synthesis and Aldec's Active-HDL Lattice Edition simulator, includes support for automotive temperature grade LatticeXP2 FPGAs, and provides the latest LatticeMico32 embedded open source microprocessor enhancements.

"This ispLEVER service pack adds a wide range of new utilities and updates that are designed to increase engineers' productivity," said Tim Schnettler, director of design tools marketing at Lattice. "For example, integration of the ORCAstra configuration interface will accelerate the all important task of real hardware tuning and debug."

About ORCAstra
The ORCAstra software is a Windows-based graphical user interface that enables configuration of the operational modes of the LatticeSC, LatticeSCM, LatticeECP2, LatticeECP2M, and LatticeXP2 FPGA families by programming control bits into on-chip registers.

This new ability to explore configuration options quickly without recompiling the FPGA design dramatically speeds design validation. For example, SERDES I/O parameters can be "tuned" interactively in the lab to maximize signal quality and performance. Configurations created in the GUI may be saved to memory and re-loaded for later use. A macro capability supports script-based configuration and testing and the GUI may be used to display system status information in real time.

About the LatticeMico32 embedded microprocessor
The LatticeMico32 core is a 32-bit soft microprocessor optimized for Lattice Field Programmable Gate Arrays (FPGAs). Lattice has released the Hardware Description Language (HDL) code for the microprocessor core and various peripheral components generated by the LatticeMico32 System, along with selected tools, in an open source format that provides design visibility, flexibility and portability.

The heart of the product is the LatticeMico32 System development tool suite that provides a fast and easy way to implement microprocessor designs from platform definition to software development and debug. This flexible microprocessor platform finds applications in a wide variety of markets including communications, consumer, computing, medical, industrial and automotive.

About the Lattice ispLEVER design tool suite
The ispLEVER Design Tool Suite is the flagship design environment for the latest Lattice FPGA products. It provides a complete set of tools for all design tasks, including project management, IP integration, design planning, place and route, in-system logic analysis and more. The ispLEVER software is provided on CD-ROM and DVD for Windows, UNIX or Linux platforms. The ispLEVER suite includes Synopsys Synplify Pro synthesis for all operating systems supported and the Active-HDL Lattice Edition simulator for Windows.

Pricing and availability
Lattice's Service Pack 1 for ispLEVER 7.1 for Windows, LINUX and UNIX users is available immediately without charge for customers with active design tool maintenance. The full ispLEVER design tool suite starts at a price of $1295 for the Windows version.