Lattice delivers RLDRAM I/II memory controller support

The LatticeSC and LatticeSCM FPGA families (collectively, the "LatticeSC/M" families) now support RLDRAM I/II rates up to 800 Mbps. The high-speed RLDRAM I and RLDRAM II memory controller IP (intellectual property) is implemented in Lattice's low-power MACO (Masked Array for Cost Optimization) structured ASIC technology.

About the LatticeSC/M FPGA family
The folks at Lattice say that their extreme-performance LatticeSC family is designed to provide the unsurpassed performance and connectivity that is essential for high-speed applications. Fabricated on Fujitsu's 90nm CMOS process technology utilizing 300mm wafers, LatticeSC FPGAs are packed with features that accelerate chip-to-chip, chip-to-memory, high-speed serial, backplane and network data path connectivity.

Integrated into the LatticeSC devices are high-channel count SERDES blocks supporting 3.8 Gbps data rates, PURESPEED parallel I/O providing 2 Gbps speed, innovative clock management structures, FPGA logic operating at 500 MHz, and massive amounts of block RAM. Lattice's Masked Array for Cost Optimization (MACO) embedded structured ASIC blocks also are available on the LatticeSCM devices, delivering pre-engineered, standard-compliant IP functions such as high-speed Memory Controllers, SPI4.2, Ethernet MACs, and PCI Express control functions developed by Lattice to shorten end-system time to market.

About MACO technology
Unlike the soft IP cores commonly used with FPGAs, the MACO IP functions are embedded into the devices, and there is no distinct IP license fee associated with their use. These enhanced memory controllers provide the industry's fastest programmable memory interfaces supporting next generation RLDRAM I/II memory devices, as well as DDR I/II and QDR II/II+ memory devices.

Lattice's ispLEVER version 7.1 software design tool suite supports a complete HDL-based design and verification flow for LatticeSCM devices, as well as other Lattice programmable device families.