Now this is really, REALLY "Cool Beans!"
For some time we've been hearing stories about a new form of FPGA that can run at blazingly fast speeds (just enter "Achronix" in the Programmable Logic DesignLine "Search" field to be presented with a series of articles).
Well, the folks at Achronix Semiconductor have finally come out of stealth mode and leapt into the center of the stage to announce that they have already begun shipping the world's fastest FPGAs.
The Speedster family, with the SPD60 (pronounced "Speedy-60") as its initial member, uses Achronix's patented picoPIPE acceleration technology to deliver speeds up to 1.5 GHz, which represents a three-fold increase in performance over the fastest existing FPGAs.
The folks at Achronix say that their early engagement customers have already found success with Speedster in applications requiring ASIC-like performance, such as networking, telecommunications, test and measurement, encryption and other high-performance applications. These types of applications are an ideal fit for the Speedster family of FPGAs.
FPGAs that run faster than ASICs?
Now hold onto your hats, because I'm about to say a scary word ... asynchronous! There, I've said it and I'm not ashamed at all. That's right; the core fabric of the Speedster FPGA is asynchronous, thereby eliminating any limitations associated with global clock distributions. The end result is that Speedster FPGAs can actually run faster than many Standard Cell ASICs as illustrated below:
Having said this, Speedster FPGAs are synchronous at their I/O interface, so they appear to be like any other chip as far as the outside world is concerned.
Existing HDL code and tools still work
Now, your knee-jerk reaction may be something like: "Good grief, I don't have the time to learn how to create asynchronous designs!" Well fear not, because you don't have to. This is where things start to become very, VERY clever.
Although it's true that the underlying Speedster fabric is asynchronous, it's also based on traditional 4-input look-up tables (LUTs), RAM blocks, multipliers, and so forth. The difference is that there aren't any registers per se; all of the elements in the Speedster fabric are separated (or connected/linked, depending on your point of view) by self-timed asynchronous micro-pipeline stages, known as picoPIPE technology.
The really, REALLY cool thing is that you don't have to tailor your HDL code (Verilog or VHDL) with an Achronix implementation in mind. Just for the sake of an example, let's suppose you are working on an existing design that you originally intended for an ASIC implementation. Let's further hazard a guess that this design involves multiple clock domains with a mixture of gated clocks and un-gated clocks. Is this going to be a problem? No worries (as they say "down under"), because the design tools will essentially discard the clocks anyway.
As an aside, this means that using Speedster FPGAs to prototype your ASIC designs is particularly easy, because you can use the same HDL code for both. But... why bother creating an ASIC at all? In many cases, you may decide that a Speedster FPGA is the better implementation solution for your particular application.
Now, one problem that we typically see when new device architectures rear their ugly heads is the need to purchase, learn, and use a weird and wonderful suite of new, proprietary, and (often) buggy design tools. Well, once again we have to take our hats off to the guys and gals at Achronix, because they've addressed this concern also...
In fact, Achronix has partnered with leading synthesis vendors to make industry-standard tools and methodologies compatible with the Speedster family. Designers can leverage their existing Verilog and VHDL designs. The Achronix CAD environment supports both Synopsys (formerly Synplicity) Synplify Pro and Mentor Graphics' Precision Synthesis tools for RTL synthesis. In addition, the Achronix CAD environment provides all the necessary tools for physical implementation, performance optimization, timing analysis, simulation, debug, and device programming.
More information about the Speedster family
The first member in the Speedster family, the SPD60, boasts 47,040 LUTs, 144 x 18Kbit Block RAMs, 735 Kbits of Distributed RAM, 98 18x18 multipliers, 8 x 5GBps SerDes, 20 x 10.3Gbps SerDes, 4 x DDR2/DDR3 Controllers, 16 PLLs, ... and the list goes on.
The Achronix picoPIPE acceleration technology speeds the way data moves through the FPGA fabric. In the absence of a global clock, the picoPIPE stages use simple handshake protocols to efficiently control data flow, resulting in significantly improved performance, all along using standard RTL for design-entry and employing familiar FPGA tools. By coupling this innovative technology with a 10.3 Gbps serializer / deserializer (SerDes) to facilitate high system throughput and integrated DDR2/DDR3 controllers for high-speed memory interface, the Speedster family provides the I/O speed to match its outstanding core performance. The device is manufactured in TSMC's high performance 65 nm G+ CMOS process.
The Speedster 10.3 Gbps SerDes supports numerous high-speed interfaces, such as PCI Express (Generations 1 and 2), gigabit Ethernet, CEI-6G, 10 Gbps backplane, XAUI, XFI, Serial Rapid IO, and Infiniband. Speedster FPGAs also include DDR2/DDR3 physical layer and controller supporting memory interface speeds of up to 1066 Mbps. standard data path interfaces, including PCI/PCI-X, SPI-4.2, SFI-4.1 and Hypertransport are also supported.
Pricing and availability
Considering the fact that they've only just officially announced themselves, the folks at Achronix have certainly hit the ground running, because they have direct sales offices in the US, Korea and Japan; furthermore, they tell me that a global sales, support, and distribution channel for Achronix FPGAs has already been established and trained in all other major markets.
Volume pricing for the Speedster FPGA family ranges from under $200 to $2500. For more information, please contact the folks at Achronix (www.achronix.com) and tell them: "Max says Hi".