The folks at Xilinx
have announced what they say is the world's first single-FPGA solution for telecommunications equipment manufacturers developing the next generation in Ethernet bridging and switching solutions.
Aimed at spurring innovation and growth in the 40- and 100-Gigabit Ethernet (GbE) market, Xilinx has added the Virtex-5 TXT platform to its high-performance family of 65-nanometer (nm) field programmable gate arrays (FPGAs).
Virtex-5 FPGA Platforms.
First we had the LX devices (not shown here), with lots of logic, lots of on-chip RAM, lots of regular GPIOs, and a reasonable amount of DSP capabilities. These were followed by the LXT platforms, which augmented the regular LX devices with a reasonable amount of high-speed serial I/Os.
Next came the SXT platforms, which really ramped up on the DSP side of things. These were followed by the FXT devices, which boosted the on-chip RAM, slightly reduced the logic and DSP, and added one or two PowerPC hard processor cores.
In the case of the newly announced TXT devices, DSP capabilities have been reduced, but the high-speed serial I/Os have been boosted to an all-time high.
The Virtex-5 TXT platform consists of two devices that are said to deliver the highest number of 6.5Gbps serial transceivers available on any FPGA, and are fully supported with application-specific IP, development tools, and reference designs for implementing high-bandwidth protocol bridging.
"The explosive growth in Internet traffic for video over IP is creating the need to rapidly scale the world's IP infrastructure. This has a direct impact on IP backbone network capacity, individual core router size, router-to-router link bandwidth, and the performance of optical transport networks used to carry traffic across wide area networks," said Dean Westman, Vice President, Communications Business at Xilinx. "Virtex-5 TXT FPGAs tackle the challenges these requirements impose on hardware designers by enabling ultra-high bandwidth communications on a power-optimized programmable platform. This is a critical step forward for the telecommunications industry, and has the potential to accelerate development of the 40GbE and 100GbE infrastructure needed to deliver multimedia services."
According Communications Industry Researchers (CIR) analyst Lawrence Gasman, the industry efforts led by the IEEE to create 40- and 100-GbE systems will result in $4.3 billion in annual revenues by 2016; "Although the new Ethernet standards will impact every segment of the network from long-haul to interconnect, the initial demand thrust is expected to come from servers, which will account for just over 40 percent of the 40/100Gbps Ethernet market by 2016. Even with 40Gbps Ethernet, there will still be a need for 100Gbps, especially for switch connections, which will represent half of the 100GbE market in 2016."
Flexible FPGA architecture
First introduced with Virtex-4 FPGA family, the ASMBL architecture enables Xilinx to rapidly develop and deploy domain-optimized silicon platforms targeted at the technical requirements of specific markets and applications. With its forty-eight (48) 6.5Gbps GTX transceivers, the new Virtex-5 TXT platform is uniquely optimized for 100 Gigabit Ethernet applications. It is designed to improve signal integrity for reliable operation of 10/100Gbps links, lower power consumption per channel for better reliability, and provide programmable support for multiple protocols, thus easily adapted to evolving standards for the interface between 100Gbps optical modules and the media access controller (MAC).
Virtex-5 TXT devices offer the only single-chip solution with built-in flexibility and re-programmability to scale as 40GbE and 100GbE hardware requirements and standards mature, while delivering the 600Gbps total bandwidth required today to build network bridges such as:
- 100GbE to 120Gbps Interlaken
- 40Gbps Quad XAUI to 50Gbps Interlaken
- OC-768 to OTU-3
- SFI-5 to 4xSFI4.2
The high-bandwidth capabilities of the Virtex-5 TXT platform are also well suited for high-performance computing and video broadcast applications. The high-transceiver count and ability to support multiple standards on a single programmable Virtex-5 TXT device delivers the flexibility, performance, and low-risk required by these markets.
Pricing and availability
Customers can immediately begin designing with Virtex-5 TXT FPGA devices using the ISE design suite service pack 3 available at www.xilinx.com/ISE. The HSEC IP core is available from Sarance Technologies (www.sarance.com).
The Virtex-5 TX150T and Virtex-5 TX240T devices will begin sampling by the end of calendar 2008 with production devices available in the first quarter of 2009. The TX150T device will list for under US$500 in 5,000 unit volumes by second half of 2009. The Virtex-5 EasyPath program supports Virtex-5 TXT devices for high-volume cost reductions. For more information, please visit: www.xilinx.com/virtex5txt.