Flexible, programmable 40 Gbps SerDes framer interface IP core

The folks at Lattice Semiconductor have just announced the availability of the 40 Gbps SERDES Framer Interface, Level 5 (SFI5) Intellectual Property (IP) Core for use in the LatticeSC and LatticeSCM (collectively, "LatticeSC/M") FPGA families. The solution utilizes seventeen SERializer/DESerializer (SERDES) channels in the LatticeSC/M devices, including the Lattice SFI5 soft IP core, and enables flexible and high performance next generation 40 Gbps systems.

The LatticeSC/M FPGA devices include 4- to 32-channels of high-speed SERDES capable of supporting data rates from 600 Mbps to 3.8 Gbps, and are said to be the industry's highest channel count SERDES-based FPGAs in production today.

The flexiPCS Physical Coding Sublayer block embedded in the devices supports an array of popular communications data protocols, including SONET/SDH, Gigabit Ethernet, Fibre Channel, 10 Gigabit Ethernet (XAUI), PCI Express and Serial RapidIO.

Additionally, the LatticeSCM FPGA family also includes pre-engineered, fully standard-compliant embedded Intellectual Property cores (SPI4.2, 1G/10G Ethernet MACs, PCI Express, Memory Controllers and CDR) implemented in Lattice's unique low power MACO (Masked Array for Cost Optimization) structured ASIC blocks. These features, along with the LatticeSC's high-speed FPGA fabric and PURESPEED I/O technology, provide an ideal platform for a variety of next generation transport applications.

The LatticeSCM family (as well as the LatticeSC family, which does not support MACO functionality but is otherwise identical) provides five logic density points between 15K and 115K LUTs, 4- to 32-channels of embedded SERDES, embedded memory capacity from 1 to 7.8 Megabits of dual-port block RAM and general-purpose 2 Gbps PURESPEED I/O ranging from 139 to 942 I/Os. Each device also features 8 analog PLLs and 12 digital DLLs and ample clock routing for optimum clock flexibility.

Lattice's MACO embedded structured ASIC blocks are available on LatticeSCM FPGA devices and deliver pre-engineered, standard-compliant IP functions developed by Lattice to shorten end-system time to market. The LatticeSC/M families of FPGAs are supported by Lattice's latest generation of design tools, the ispLEVER version 7.2 software design tool suite.

Lattice SFI5 IP Core
The SFI5 IP solution is available as a downloadable core from the Lattice Semiconductor website. This bundle demonstrates the power of the LatticeSC family's SERDES technology as well as its hard IP blocks. Key features of the IP bundle include:

• Full compliance to the Optical Internetworking Forum (OIF) Implementation Agreement OIF-SFI5-01.02
• Data path uses 17 SERDES transceivers operating in 8-bit only mode
• Sixteen 16-bit wide internal receive and transmit data paths
• Supported through the ispLEVER IPexpress tool for easy user configuration and parameterization
• Reference design suitable for use on the Lattice Semiconductor SFI5 Evaluation Board with SERDES channels running at 2.5 Gbps
• Reference design uses the Reveal Logic Analyzer to observe circuit operation
• User-settable parameters to select the allowed number of framing errors for the deskew channel framer to go into or out of locked state

The IP core and reference design are provided to customers at no charge. An evaluation copy of the bundle is available now and can be downloaded by registered Lattice design tool users with current maintenance agreements without charge from www.latticesemi.com/products/intellectualproperty.