The C-to-Silicon Compiler is claimed to improve designer productivity up to 10 times in creating and re-using system-on-chip IP. Originally focused on ASICs, this new version of the C-to-Silicon Compiler delivers the same productivity benefits to designers of system-on-chip IP blocks targeting Altera and Xilinx FPGAs.

"We are starting to use C-to-Silicon Compiler in several production ASIC designs, and are recommending it to the other Hitachi design groups," said Toru Hiyama, general manager, MONOZUKURI Innovation Operation, Hardware MONOZUKURI Division at Hitachi, Ltd. "We requested Cadence for FPGA synthesis support earlier last year, expecting more designers would use C-to-Silicon Compiler not only for ASIC designs but also for high-priority FPGA designs. We are very pleased to see FPGA support capability available on C-to-Silicon Compiler, and the quality of results using C-to-Silicon Compiler is very promising."

The C-to-Silicon Compiler was launched in July 2008 with two unique capabilities in high-level synthesis, Embedded Logic Synthesis (ELS), and a Behavior Structure Timing (BST) database. ELS uses Cadence Encounter RTL Compiler global synthesis to help ensure high accuracy and high-quality implementation results. The BST database enables design teams to perform true incremental synthesis – for example, re-synthesizing only the parts of the design that changed while leaving the rest of the design untouched. The latest release of the C-to-Silicon Compiler extends these capabilities from ASICs to FPGAs, with the same benefits.

The Cadence C-to-Silicon Compiler is available in limited production, and is designed to work with the Altera's Quartus II software and Xilinx Synthesis Technology FPGA-synthesis tools available from Altera and Xilinx, respectively. Its capabilities will be demonstrated in the Cadence booth during the Electronic Design and Solution Fair (EDSF) Jan. 22-23 in Yokohama, Japan.