The folks at Mentor Graphics
say that the inFact intelligent testbench automation tool, which applies universally to FPGA and ASIC
designs, now provides full support for the Open Verification Methodology (OVM 2.0).
The inFact tool uses systematic algorithms, which allow it to rapidly produce unique, non-redundant test cases. When broad test coverage is important, the inFact tool's ability to move linearly towards coverage closure can reduce test repetition by 10x, providing more complete test, more quickly.
The inFact tool provides plug-and-play interoperability with OVM compliant verification components and sequences, allowing easy creation of intelligent testbenches. OVM sequences provide a powerful modular mechanism for users to describe interesting series of stimulus transactions in a reusable way. Sequences are defined outside the component hierarchy, presenting a straightforward way to develop both directed and constrained-random test cases, without the test writer needing to know the details of how the underlying testbench was developed. Sequences are also hierarchical, so they easily model layered protocols and can also control the interactions of other sequences.
Using an approach such as the graph-based intelligent testbench automation found in the inFact tool to efficiently create verification scenarios and stimuli is a powerful way to enhance advanced verification environments. The inFact tool sequences may be used to augment or replace user-developed sequences in OVM, adding even more horsepower to your verification. When coupled with a proven methodology like OVM, that ties all the tools together, inFact accelerates coverage closure, reduces common verification headaches, and frees up resources to focus on more ambitious verification plans and higher levels of functional coverage. Ultimately, this enables the verification team to exercise the device in a far more comprehensive manner, thereby reducing defects.
About the Open Verification Methodology (OVM)
The OVM is based on the IEEE 1800 SystemVerilog standard and supports design and verification engineers developing advanced verification environments that offer higher levels of integration and portability of Verification IP.
The methodology is non-vendor specific and is interoperable with multiple languages and simulators. The OVM is fully open, and includes a robust class library and source code that is available for download. Visit www.ovmworld.org for more information.