Lattice rolls 65-nm FPGAs, clock chips

As part of the moves, Lattice (Hillsboro, Ore.) has introduced its first 65-nm field-programmable gate arrays (FPGAs) in the market. Aimed for the emerging ''mid-range'' sector, the LatticeECP3 line claims to be the industry's lowest-power, Serdes-capable FPGAs. Serdes or serializer/deserializer chips are at the heart of many high-speed designs today.

The company has also expanded its family of differential clock distribution ICs. And it also announced the availability of 15 new reference designs and a new $59 development kit for its existing MachXO PLD family.

A key to the introduction is the LatticeECP3 line, which is based on a 65-nm process from its key foundry partner--Japan's Fujitsu Ltd. Until now, Lattice's mid-range and high-end parts were based on 90-nm technology.

The new line features a multi-protocol 3.2-gigabit-per-second Serdes with XAUI jitter compliance, a DDR3 memory interface, digital signal processing (DSP) capabilities, on-chip memory and from 17K to 149K logic elements.

The products compete in the so-called mid-range segment, which encompasses mainstream and cost-sensitive applications in the networking, storage, video, wireless and wireline sectors.

In the mid-range FPGA market, Lattice competes against Actel, Altera and Xilinx. The new LatticeECP3 line is aimed to pre-empt new, mid-range introductions from Altera Corp. and Xilinx Inc. Recently, Altera rolled out a 40-nm version of its mid-range Arria FPGAs, while Xilinx separately introduced the Spartan-6 products, based on 45-nm technology.

While it appears Altera and Xilinx beat Lattice to the punch, the Hillsboro-based company claims to have the upper hand in the mid-range market. Lattice has been shipping mid-range FPGAs for some time.

Lattice has also been quietly sampling the LatticeECP3 line since September, but it did not disclose the products until now. Unlike some of its rivals--which tend to pre-announce products--Lattice takes a more conservative approach in the market, said Shakeel Peera, director of strategic marketing for SRAM FPGAs.

''When you compete against the 800-pound gorillas, it doesn't make sense to pre-announce products,'' Peera said. ''We only announce products when they are available.''

The strategy makes sense for Lattice, but it also creates less buzz for its new products, analysts said. Lattice, the world's third largest FPGA vendor, also appears to be behind its rivals in process technology.

"Being on leading process technologies doesn't mean you have any power advantages,'' he said. The LatticeECP3 family reduces static power consumption by 80 percent and total power consumption by over 50 percent for typical designs, compared to competitive FPGAs, according to the company.

Lattice also claims it is driving the mid-range FPGA market, which is becoming a more important sector in the PLD arena. Many of today's new and emerging applications ''can be met with mid-range FPGAs,'' Peera said.

''There is room for high-end FPGAs, (but) premium FPGAs are a thing of the past for most applications,'' he said. ''They are pricey. They also take up a lot of power consumption.''

Realizing the trend at the high-end, Altera and Xilinx are now expanding aggressively into the mid-range FPGA segments. In some respects, the two FPGA giants are emulating and have validated Lattice's strategy, said Doug Hunter, vice president of corporate marketing at Lattice.

''We are flattered by (the recent announcements) of Altera and Xilinx,'' Hunter said, vowing that Lattice ''would maintain its lead in mid-range FPGAs.''

The introductions by Lattice and other FPGA vendors comes amid one of the worst downturns in the IC industry. FPGA vendors are seeing a drop in demand, but design activity remains strong. "I think we'll see a back-half recovery,'' he said. ''The economy favors PLDs over ASICs and ASSPs.''

Seeking to capture new business amid the downturn, Lattice has rolled out the LatticeECP3 line of five devices. The previous mid-range line, dubbed ECP2M, were rolled out in 2006. The ECP2M line features from 6k-to-95K logic elements, 5.3 Mbits embedded RAM, DDR/DDR2 memory interfaces, 168 18 x 18 bit multipliers and 16 Serdes channels running at 3.2-Gbps.

In comparison, the LatticeECP3 features from 17k-to-150K logic elements, 7 Mbits embedded RAM, DDR/DDR2/DDR3 memory interfaces and 320 18 x 18 bit multipliers.

The entry-level ECP3-17 part features 17k logic elements, 552 Kbits embedded RAM, 24 18 x 18 bit multipliers and 4 Serdes channels running at 3.2-Gbps. The high-end ECP3-150 part features 149k logic elements, 6.85 Mbits embedded RAM, 320 18 x 18 bit multipliers and 16 Serdes channels running at 3.2-Gbps.

It also includes the company's second-generation Serdes, which has data rates from 250-Mbps to 3.2-Gbps and a power consumption of 90-mW per channel. It is said to have 10-GbE XAUI jitter compliance and the ability to mix and match multiple protocols on each Serdes quad. This includes PCI Express, CPRI, OBSAI, XAUI, Serial RapidIO and Gigabit Ethernet.

The devices also comply with the SMPTE Serial Digital Interface standard, with the ability to support 3G, HD and SD video broadcast signals on each Serdes channel. The triple rate support is performed without any oversampling technique, consuming the least possible amount of power, according to Lattice.

The devices also consist of a third-generation DSP architecture, dubbed sysDSP. The DSP blocks consists of up to 36 x 36 multipliers and accumulate functions running at 500-MHz. The DSP slices also feature cascadability for implementing wide ALU and adder tree functions without the performance bottlenecks of FPGA logic.

Toggling at 1-Gbps, the LatticeECP3 FPGAs also feature the fastest LVDS I/O available in a mid-range FPGA family. Production devices are available now. In 25,000-unit volume and the FN484 wirebond package, the LatticeECP3-70 is priced as low as $35 and the LatticeECP3-95 is priced as low as $50.

The LatticeECP3 FPGA family is supported by the ispLEVER design tool suite, version 7.2 Service Pack 1. It provides a complete set of tools for all design tasks, including project management, IP integration, design planning, place and route, in-system logic analysis and more. The ispLEVER design tool suite includes Synopsys' Synplify Pro synthesis for all operating systems supported and Aldec's Active-HDL Lattice Edition simulator for Windows.