SAN FRANCISCO—Lattice Semiconductor Corp. Monday (June 15) announced the availability of Service Pack 2 (SP2) for Version 7.2 of the company's ispLever FPGA design tool suite, the flagship design environment for the latest Lattice products.

According to Lattice (Hillsboro, Ore.), SP2 is an important update for users of LatticeECP3 devices and also includes support for new LatticeXP2 devices. The update boosts DSP application performance in LatticeECP3 devices and gives designers greater confidence that the board-level behavior of a design will match what the tools report, according to the company.

SP2 updates design support, which was first made available in ispLever 7.2 Service Pack 1, Lattice said. SP2 updates the device values to production characterized silicon for the LatticeECP3-70 and ECP3-95 devices, the company said.

With SP2, static timing analysis, power and switching output noise will report results that even more accurately reflect the behavior of the actual production device. Moreover, PCS/Serdes calibration settings used for the supported IO protocols have been tuned to provide more robust behavior, according to Lattice.

The sysDSP block support also has been enhanced to include higher performance modes of primitive blocks targeted at specific applications, such as FIR filters, decimators, interpolators, matrix multiplication and video applications, Lattice said. These modes are made possible by the enhanced cascade support in the LatticeECP3 devices' sysDSP architecture, according to the company.

SP 2 also supports the recently announced industrial temperature qualified, non-volatile LatticeXP2 devices that are available now in low-cost, small-footprint BGA or QFP packaging, Lattice said.

The ispLever 7.2 Service Pack 2 tool suite for Windows, LINUX and UNIX users is available immediately without charge for customers with active design tool maintenance contracts, Lattice said. Pricing for the full ispLever design tool suite starts at $1,295 for the Windows version, the company said.