Altera enhances security in extended Cyclone-III FPGA family

LONDON — Altera Corp. (San Jose, Calif.) has introduced the Cyclone-III LS family of FPGAs with enhanced security features. The devices are made on a 60-nm process technology from TSMC and offer 0.25W of static power consumption for 200,000 logic elements.

The original Cyclone-III members were launched on 65-nm CMOS from TSMC. So te shrink has allowed a larger device, an improved power consumption and clock frequency to be extended beyond 200-MHz but not all at the same time.

The security features include a design blanking feature that can be programmably invoked, anti-tamper, JTAG port protection, a 32-bit cyclic redundancy check to monitor the internal configuration, an internal PLL so that missed clock cycles can be used to invoke device blanking, and 256-bit AES key for use in encrypted configuration downloads.

The Cyclone-III LS also allows for physical design separation to allow physically separated redundant designs to be contained in a single device. However, the device does not support partial reconfiguration.

Cyclone-III LS is being offered particularly for military and industrial applications, such as crypto subsystems and software-defined radio. The Quartus II design software has already been extended to support Cyclone-III LS, Altera said.