Altera (San Jose, Calif.) said it is the first FPGA vendor to offer a Serial RapidIO intellectual property (IP) core that is fully qualified by Riolab.

Riolab is an independent RapidIO interoperability testing facility. DIL-3 is Riolab's final stage of device interoperability testing and ensures Altera's internally developed Serial RapidIO IP is interoperable with components, systems and software using RapidIO technology, according to Altera. The IP core works with the company's Arria, Cyclone and Stratix FPGAs and HardCopy ASICs.

Altera's Serial RapidIO MegaCore function is designed to the RapidIO interconnect specification version 1.3. The core supports x1 and x4 lane widths at 1.25-Gbps, 2.5-Gbps and 3.125-Gbps lane rates, and allows for physical-, transport- and logical-layer separation, Altera said. The endpoint IP core comes with test benches that provide proven interoperability with leading digital signal processor and switch vendors, the company said.

The Serial RapidIO MegaCore function is available for download on Altera's website as part of the combined Quartus II Software/Altera MegaCore release. The function is also supported with Altera's Quartus II software version 9.0, and is available as encrypted IP or as source code.