Averant will integrate the Axiom Designer debugging GUI with Solidify to ease the challenges of formal property verification. Axiom's MPSim simulator will also be used in the flow to demonstrate failed properties to the user. Axiom, formerly @HDL, introduced the MPSim SystemVerilog simulator in May 2005.

Axiom's Designer supports simulation debugging, testbench debugging, code and functional coverage, formal verification, multi-clock domain verification, and design rule checking debugging. MPSim is a multi-CPU simulator.

Averant's Solidify provices property-based design verification, protocol verification, timing constraint verification, and automatic design checks. At the Design Automation Conference in July last year, Averant rolled out Solidify 4.0, offering an ability to trade off completeness and accuracy against CPU time. A new guided proof system claimed to enable designers to use the tool to conduct rapid "bug hunting" exercises early on in the design cycle, then move to more exhaustive proofs of assertions later in the design cycle. Solidify 4.0 also supports SystemVerilog assertions.

"The combination of our leading-edge formal verification technology with Designer's unique debug capabilities will significantly amplify the use and adoption of formal model checking technology for design and verification engineers," said Ramin Hojati, Averant president, in a statement.