Kit From Cadence Supports Functional Verification

Venice, Florida — Cadence Design Systems, Inc. announced a verification kit for wireless and consumer system-on-chip (SoC) design. It aims to enable engineers to adopt advanced verification techniques with reduced risk and deployment effort and meet time-to-market requirements. The Cadence' SoC Functional Verification Kit extends from block-level verification to chip- and system- level advanced verification and includes automated methodologies for implementation and management. The kit provides complete example verification plans, transaction-level and cycle-accurate models, design and verification IP, scripts and libraries -- all proven on a wireless segment representative design and delivered through applicability consulting.

The kit is the latest entry into a family of products that package tools, IP, methods, and consulting into one deliverable from Cadence with the aim to become a partner with the customer in tackling difficult design and verification problems. This kit addresses key challenges engineers face when designing and verifying SoC designs: ensuring comprehensive verification of the design, enabling re-use, managing low-power modes typical in today's SoCs, ensuring hardware-dependent software coverage, and accomplishing the verification within very stringent time-to-market timelines.

The applicability consulting included with the kit provides complete and interactive guidance for performing predictable and repeatable verification of blocks, clusters, full chips, and SoCs, and enables design teams to quickly and easily adopt the Cadence Incisive® Plan-to-Closure Methodology.

The SoC Functional Verification Kit includes design and verification IP from Cadence and third parties, including a high-speed model of the ARM968E-S^TM processor, AMBA® PrimeCell IP including interconnect and peripherals, and the ARM RealView® Development Suite debugger, USB 2.0 from ChipIdea, and 802.11 from WiPro. The kit includes three main flows: architectural, RTL block to chip, and system-level. Users can implement the entire kit as an integrated flow, or may select flows individually. Also included are 13 workshop modules and over 40 hands-on labs which engineers can use to incrementally improve their verification productivity.

The Cadence Incisive Plan-to-Closure Methodology will support the Open Verification Methodology or OVM in Q4 this year. The OVM is based on Cadence's Incisive Plan-to-Closure URM module and Mentor's Advanced Verification Methodology module.