Synopsys Brings IC Design and Manufacturing Test Closer

Venice, Florida — As if Design for Test (DFT) methods needed more reasons to be considered a critical aspect of today's IC design, three of the four largest EDA companies have recently announced improvements in their Test for Manufacturing tools to help test engineers with the difficult task of verifying the functionality of IC that employ the advanced design methods required by 65nm and 45nm processes. Following announcements by Mentor Graphics (see the article ), and Magma Design Automation introduction of Talus ATPG and Talus ATPG-X (article here), Synopsys has just announced an extension to its Galaxy^TM test solution.

Synopsys has extended low power management capabilities in the tool to reduce the time and effort needed to generate power-aware manufacturing tests for integrated circuits (ICs). The TetraMAX® automatic test pattern generation (ATPG) solution now creates tests reflecting designers' power budgets, and the DFT MAX scan compression product further automates integration of design-for-test (DFT) structures in designs that deploy advanced low power management techniques.

Scan testing typically increases transistor switching activity inside ICs by many times their peak functional mode levels, leading to excessive power consumption. Too much power consumption during test can lead to unpredictable test results, including the failure of fully-functional devices at the tester, and unnecessary yield loss. Ad-hoc power reduction techniques for test, however, require considerable engineering effort to implement seamlessly with scan compression, used for reducing test data volume. New functionality in the TetraMAX product limits power consumption during test by automatically reducing switching activity to levels consistent with normal operation, based on designer-specified power budgets.

"Synopsys' TetraMAX small delay defect pattern generation capability detects timing problems associated with paths having very small timing margins," stated Dr. Tom Williams, Synopsys Fellow. "Because excessive power consumption can affect the delays of such paths, automation to manage it is now included in TetraMAX as part of Synopsys' comprehensive ATPG solution for achieving ultra-high test quality."

DFT MAX power optimization aims to minimize the number of scan chain connections that cross voltage domains, and lower the area impact of DFT by reducing the number of required level shifters and power isolation cells. Power intent affecting both scan domains and power domains, specified in the Accellera standard Unified Power Format (UPF), is now preserved throughout the Galaxy platform flow, from synthesis through physical implementation and sign-off.

In a related release, the company has also announced the commercial release of the Odyssey DFT. The Odyssey yield management software analyzes diverse datasets needed for product yield enhancement. The TetraMAX® automatic test pattern generation (ATPG) solution creates high-quality manufacturing tests and identifies logic in a design that could contribute to observed tester failures. TetraMAX failure diagnostics data is exported to the new Odyssey DFT module to facilitate failure analysis and yield improvement of fabricated devices.