Venice, Florida — Mentor Graphics Corporation announced that its HDL DesignerTM
Series product has been extended to provide a platform for implementing SystemVerilog. The product is used to accelerate register transfer level (RTL) design reuse and optimize design creation, synthesis, and verification processes for complex application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) designs. The HDL Designer Series already supports the use of VHDL, C/C++, PSL, and Verilog, in a mixed-languages environment.
Unlike traditional HDLs (hardware description language), SystemVerilog introduces an object-oriented design style that offers a plethora of new language features. As a result, designer productivity can be improved by automatically evaluating RTL code quality, design integrity and analysis, and design visualization for effective design reuse.
The HDL Designer Series product supports the following SystemVerilog features in this current release:
- Mixed-language and dialect support
- Assertions and coverage reports
- The ability to instance SV1800 components with V95-compatible port descriptions in V95 BD/IBD to create structural design
- Auto detects, dialect, and top-of-design
- Where Used and Where Bound reports
- Additional Browser Objects: SystemVerilog packages, program blocks, interfaces, and classes
- Hierarchy Browser additions: program blocks, interfaces, and class instances
- File templates for new objects, such as packages and classes
The HDL Designer solution with SystemVerilog is available now, with pricing starting at $6,900 (USD).