Venice, Florida — Actel Corporation's FPGA devices have for a long time offered low power solutions to designers. Now, extending the company's solutions for saving power at the chip and system levels, Actel Corporation has rolled out version 8.1 of its LiberoTM
Integrated Design Environment (IDE) with significant new features, such as power-driven layout, that enable designers to further optimize designs to reduce dynamic power consumption by as much as 30 percent for a typical design.
With the power analysis capabilities built into Libero's SmartPower tool, the enhanced analysis environment gives users an understanding of power usage in all functional modes of the design. In addition, a battery life estimation feature allows designers to estimate battery life based on their FPGA design power profile.
Actel has used EDA partners to offer a complete design flow to its customers. The new version of Libero integrates with Modelsim form Mentor for logic simulation and verification, and with Synplicity's Synplify for logic synthesis. The design entry portion of the IDE, developed by Actel uses Verific Design Automation's Verilog and VHDL parsers, analyzers and elaborators to create and automatically abstract block-based system designs into synthesis-ready VHDL or Verilog components.
The new version of Libero supports all of the company's low-power families, including the ultra low-power Actel's IGLOO FPGAs and the mixed-signal Actel Fusion Programmable System Chips (PSCs).
Power-Driven Layout and Battery Life Estimation
A new option in Libero utilizes SmartPower's design analysis data for power-driven layout, to enable users to realize dynamic power savings through the reduction of the capacitive loading of the nets. While average IGLOO power consumption is reduced by 13 percent, some designs can reduce consumption by as much as 30 percent.
In addition, SmartPower provides designers the ability to create power profiles to help estimate necessary power supply and battery requirements. Defined by the user, the power profile is the percent of time the FPGA will be in a combination of custom or functional modes, such as Active, Standby, or Flash*Freeze.
To provide battery life estimation for portable or handheld designs, for example, the user inputs the desired battery's current capacity as well as the power profile of the FPGA. SmartPower then displays the expected battery life as well as a realistic and accurate report of power consumption based on the true power profile of the target FPGA.
The Libero IDE v8.1 also features enhanced SmartPower functionality, which enables analysis of the entire FPGA as well as specific portions of the device or design, such as clock domains, switching cycles, and spurious transitions, which individually contribute to overall power consumption of the device. A cycle-accurate power analysis option, for example, allows designers to look at peak power per clock cycle as well as the average power for the entire simulation.
The switching analysis option in the SmartPower tool identifies "hazards," or spurious transitions, that contribute to higher power consumption, allowing the user to address them and make corrections to reduce the power consumption. Actel maintains that in a typical design, hazards can account for as much as 20 percent of the power consumed. In some circuits, such as combinational adders, the power dissipation caused by spurious transitions can be as high as 70 percent of the total power.
The Actel Libero IDE 8.1 Platinum edition is available on Windows and Linux platforms for $2495. A limited feature Gold edition is available on Windows for free. All editions are one-year renewable licenses.