Venice, Florida — Mentor Graphics Corporation, continuing to make progress in the Physical IC design market after its acquisition of Sierra a few months ago, has announced new technology in its Olympus-SoCTM
place and route product that accelerates signal integrity(SI) closure and improves the reliability of manufactured silicon. Competition in this EDA market is increasing as designers find meeting new process technologies requirements extremely demanding. Customers designing at 65/45nm are experiencing a significant increase in SI related timing violations due to increasing dominance of lateral wire capacitance. An explosion in the number of mode and corner scenarios that must be addressed exacerbates the problem, significantly increasing the time to design closure.
Sierra had begun work on the Multi-Corner, Multi-Mode (MCMM) capability of Olympus' Static Timing Analysis (STA) in 2005. The engine, now proven by a number of successful tapeouts, concurrently computes delay shift and glitch for any number of mode/corner scenarios in a single pass. MCMM analysis enables customers to address reliability issues such as crosstalk delay, glitch, low power, and electromigration, traditionally DFM issues, and thus reduces the time to achieve design closure. The Olympus-SoC product's detailed routing and optimization engines have been enhanced to help eliminate SI violations concurrently over all variation scenarios.
Current solutions are limited due to the inability of the core STA engines to represent more than a single mode/corner combination for SI analysis. This severely hampers design teams who are forced to run several iterations with a lot of manual intervention.
Mentor's Place and Route division has implemented a new technique to concurrently compute and maintain mode/corner-specific delay shift, glitch, power, and electromigration (EM) data in a single analysis run. The solution includes several enabling technologies:
- Per clock, per corner, and per mode timing window computation
- Fast incremental SI updates over all mode/corners concurrently during implementation
- Routing techniques such as SI driven track assignment, wire spreading, and track reordering
- SI bottleneck identification for directed concurrent delta-delay, delta-slew, glitch optimization
The new SI module is available for a yearly license price of $250,000 to current Olympus-SoC customers. New customers will find that the base price of the Olympus-SoC product that contains the new SI engine is above the $750,000 mark for a yearly license.
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