Catapult C and SLEC get integrated flow

Venice, Florida — One of the obstacles to wider acceptance of ESL design methods has been the lack of an automated transition between system level and RTL design. Higher level synthesis tools, like Catapult C from Mentor and Cynthesizer from Forte are providing a way to transform C and SystemC descriptions, respectively, into RTL netlists, but up to now, there was no automatic way to verify the equivalence of the two descriptions of the same circuit. Calypto Design Systems and Mentor Graphics have announced the integration of Calypto's SLEC logic equivalence checking tool with Catapult C, the synthesis product that allows designers using a dialect of C or C++ to describe the functionality of an electronic circuit at the system level to automatically synthesize it to RTL.

This new electronic system level (ESL) hardware design and verification flow has been proven during trials at customer sites throughout the world and recently by STARC, the integrated flow is effective at synthesizing high-quality designs from pure ANSI C++ to RTL, and formally verifying that the resulting RTL design is functionally correct. According to Mitch Dale, Director of Product Marketing at Calypto, designers in the US and Europe prefer using C or C++ for system level design, while in Japan SystemC is the preferred language for the task. Although STARC is a Japanese research consortium, Mr. Dale does not consider its adoption of Catapult C and SLEC as an indication that Japanese designers are ready to change their methodology.

The two tools offer an integrated solution for ANSI C++ synthesis and verification. The Catapult C Synthesis tool enables hardware designers to create optimized RTL descriptions. Calypto's SLEC verifies that RTL designs are functionally equivalent to system-level models without testbenches or assertions. SLEC uses sequential analysis techniques to verify Catapult C's RTL output functionally matches the original ANSI C++ source. With this integration, the Catapult C Synthesis tool users can automatically generate RTL from a pure ANSI C++ description, and then create the setup scripts to launch the SLEC verification environment. This allows users to verify equivalence between the pure ANSI C++ and RTL descriptions quickly as well as verify additional design optimizations before handoff for final integrated circuit implementation.

To support the integration of SLEC with high level synthesis tools Calypto has created a new product, HLS, that is an option to the SLEC product. HLS is available immediately for the US list price of $50,000 for a one-year time-based license.