Magma Releases a Titan

Venice, Florida — Magma® Design Automation Inc. today announced Titan^TM, a full-chip mixed-signal design, analysis and verification platform. Titan tightly integrates mixed-signal implementation with digital implementation, circuit simulation, transistor-level extraction and verification - aiming to significantly increase the efficiency and productivity of analog designers.

"With Talus for digital design and Titan for mixed signal, we have achieved a level of integration that the electronic design automation industry has never before provided chip designers." Rajeev Madhavan, Magma chairman and chief executive officer, stated.

Because Titan is based on Magma's unified data model, it works seamlessly with Magma's Talus® digital IC implementation, FineSim^TM Pro circuit simulation, Quartz DRC and Quartz LVS physical verification products and transistor-level extraction. This results in analog and digital design teams ability to more readily collaborate since they now have clear visibility into their counterparts' design space.

An Evolution in Analog/Mixed-Signal Design Many articles and editorials in the industry press lately have pointed out the need for significant improvements in the efficiency of analog design methods. Analog integrated circuits are still largely full-custom and are painstakingly crafted by hand. In addition to being time-consuming and prone to error, and transistor-level design style does not allow an existing design to be easily transferred to a new foundry or process/technology node. Instead, the migration of such a design effectively requires the circuit to be re-implemented from the ground up.

With Titan, analog designers will still apply their expertise in defining the first circuit topology, but porting to new nodes will be significantly easier. In traditional flows, chip finishing - the point at which the digital and analog blocks of a design are placed and routed together - is a time-consuming and manual task.

Titan offers an integrated simulation environment using the FineSim circuit simulator, along with links to parasitic extraction. When coupled with schematic driven layout, analog circuit optimization, and analog placement-and-routing, Titan aims to provide a level of efficiency in the analog design domain that is similar to that of the digital domain. For true mixed-signal design, the FineSim interface also supports full-chip circuit simulation, offering SPICE-level accuracy for the analog portions of the design and fast SPICE-level accuracy for the digital portions of the design. This ensures that the analog/digital interfaces are well simulated and verified before committing the chip to silicon.

Chip Finishing Tool
Titan Chip Finishing, the first product to be released on this platform, provides complete and automated chip finishing capabilities. This product integrates mixed-signal layout with the Talus place-and-route capabilities. It can manipulate the largest designs with ease, automates analog and special net routing through an efficient constraints-based approach and makes all mixed-signal layout changes immediately available for physical and timing verification sign-off analysis through a live interface with Talus, Quartz DRC and Quartz LVS. Titan Chip Finishing can implement late engineering change orders (ECOs) that affect both analog and standard-cell components without significantly delaying the schedule.

Titan Chip Finishing is available now. A white paper: "The Titan Unified, Automated, Full-Chip Mixed-Signal Design Solution" white paper is available at Titan Platform .