The new product introduces advanced timing closure analysis and RTL testability improvement for deep submicron (DSM) defects associated with at-speed testing. It provides accurate RTL fault coverage estimation for transition delay testing, together with diagnostics for low fault coverage, early in the design flow, to achieve high test quality with minimum design iterations.
Atrenta is unveiling the new SpyGlass-DFT DSM product at this year's Design, Automation & Test in Europe (DATE) conference.

At-speed Testing
The test clocks in traditional stuck-at testing are designed to run on test equipment at frequencies lower than the system speed. At-speed testing requires test clocks to be generated at the system speed and these clocks are often shared with functional clocks from a phase locked loop (PLL) clock source. The additional test clocking circuitry affects functional clock skew and thus the timing closure of the design. SpyGlass-DFT DSM is designed to specifically address the problems associated with timing closure due to at-speed DFT.

At-speed tests often result in lower than required fault coverage, even with full-scan and high (greater than 99%) stuck-at coverage. Identifying reasons for low at-speed coverage at the ATPG stage is too late to make changes to the design and affects schedules significantly. The new product identifies causes of low at-speed coverage at RTL and helps achieve quick turnaround times.

Pricing and Availability
The SpyGlass-DFT DSM product will be available in SpyGlass version 4.0, scheduled for release in April 2008. The U.S. list price is $75,000 for a one-year time based license.

See also:
Timing Constraints Generation Technology