Cadence introduces constraint-driven HDI design flow for PCB

Venice, Florida — Cadence Design Systems, Inc. announced improvements to the Cadence Allegro and OrCAD families of products aimed at boosting performance and productivity through new features and functionality. Part of the Cadence SPB 16.2 release, it offers a number of improvements for designers using high-density interconnect (HDI).

New technology introduced in Allegro PCB for HDI designs includes new objects, an extensive set of new rules for micro-vias, an enhanced via-transition use model, and changes to the entire PCB design flow to enable a comprehensive constraint-driven HDI design flow. Design partitioning has been enhanced with new capabilities for partitioning the design horizontally and adding soft boundaries to allow users to work in parallel more efficiently, further shortening the design cycle.

Customers can shorten their time to market and reduce development costs for high-frequency signals such as those found in PCI Express 2.0, Serial ATA II, SAS II. Using Allegro PCB SI users can quickly and accurately simulate and validate for BER compliance using new and advanced eye mask capabilities, high-frequency field solver technology. In addition, Allegro PCB SI provides simulation support for interoperable, multi-vendor IBIS 5.0 AMI-compliant transceivers.

With the layout-driven RF PCB design capability introduced in the new release, users can eliminate the need to manually update schematics for RF circuit elements added into the layout. Combined with an improved bi-directional integration with Agilent's ADS environment, the Allegro PCB RF option allows users to shorten time to create mixed-signal digital-analog-RF designs.

OrCAD Capture boasts productivity and usability improvements including an updated GUI, enhanced search capabilities and new capability for designing-in FPGAs. New FPGA design-in features include the ability to create split symbols, import and export FPGA pin assignments for leading FPGA vendors tools, and ease-of-use improvements for supporting the ECO process for FPGAs.

Finally, engineers can specify and embed physical and spacing constraints for critical high-speed nets in the design to improve chances of first-time success while eliminating traditional error-prone verbal, email and spreadsheet-based communication. This can help shorten design cycles and eliminate unnecessary iterations between hardware designers and PCB layout designers.

SPB 16.2 will be available n November 2008. Customers can see demos of Allegro PCB and IC packaging/SiP flows at the CDNLive! Silicon Valley conference Sept. 9-11. SPB 16.2 also will be demonstrated at the EMA booth at the PCB West in Santa Clara Sept 14-19.