Cadence tackles issues in IC package/SiP design

The announced release of SPB 16.2, due in November of this year, from Cadence Design Systems, contains additions focused on addressing current and emerging chip package design challenges. This latest release delivers advanced IC package/system-in-package (SiP) miniaturization, design cycle reduction and DFM-driven design, along with a new power integrity modeling solution. These new capabilities can boost productivity of digital, analog, RF and mixed-signal IC package designers involved in single and multi-die packages/SiPs.

Design teams can expect improvements in the reduction in overall package size through the introduction of rules and constraint-driven automation capabilities that address the design methodology of high-density interconnect (HDI) substrate manufacturing that is a key enabler for miniaturization and increased functional density. Overall design time can be reduced through the enablement of team-based design, where multiple designers can work concurrently on the same design in order to reduce design cycle times and speed time to market.

With today's focus on low-power design, especially in wireless and battery-powered devices, an efficient package power delivery network (PDN) is critical for meeting power-management goals. The new power integrity technology allows designers to efficiently address the power-delivery design goals of sufficiency, efficiency and stability.

In addition, through an agreement with Kulicke & Soffa, Cadence enables DFM-driven wirebond design by using Kulicke & Soffa-verified wirebond IP profile libraries, increasing yield and reducing manufacturing delays.

Current Cadence customers can see demos of Allegro PCB and IC packaging/SiP flows at the CDNLive! Silicon Valley conference Sept. 9-11. SPB 16.2 also will be demonstrated at the EMA booth at the PCB West in Santa Clara Sept 14-19.