Mentor releases parallel timing analysis and optimization technology

Venice, Florida — Although microprocessors vendors continue to focus their efforts to produce chips with an ever increasing number of CPUs per die, their efforts have little value unless the software is engineered for parallel processing. Mentor Graphics has announced the availability of new task-oriented parallelism technology in the Mentor Graphics Olympus-SoC place-and-route system that allows timing analysis and optimization tasks to run in parallel. Mentor's research has shown, as Figure 1 indicates that timing analysis consumes the majority of CPU resources. According to benchmarks run by Mentor the technology delivers up to 7X improvement in timing analysis run times, and up to 4X improvement in design closure times using eight CPU cores.

1. Runtime for each place and route stage due to 1) timing analysis and optimization -- green, and 2) to tasks performed by other engines (placement, CTS, or routing) -- red.

Leading edge integrated circuits require exponentially increasing processing power to reach physical design closure within tight time-to-market schedules. Design sizes continue to increase, complicated by manufacturing variability and signal integrity issues that require closure over many design and process modes and corners. The best way to gain additional speed is to apply the full power of multicore processors to the most compute-intensive aspect of the flow -- timing analysis and optimization related tasks. However, traditional place-and-route architectures are not able to take full advantage of multiple processors within the timing kernel, severely limiting their scalability on multicore platforms.

The Olympus-SoC place-and-route system addresses this challenge with a combination of technologies collectively referred to as task-oriented parallelism. Mentor's task-oriented parallelism technology is a fine-grained, lockless technique that for the first time allows parallelization of the most compute intensive analysis and optimization tasks within the place-and-route timing kernel. A compact data structure with an unlimited number of virtual timing graphs makes the Olympus-SoC system inherently efficient for complex MCMM analysis. To fully utilize advanced multicore processors, the Olympus-SoC system employs sophisticated dataflow analysis that allows parasitic extraction, delay, MCMM signal integrity (SI), timing, and power analysis tasks to be done in parallel on many CPUs without the locking and synchronization overhead inherent in traditional architectures. In addition, it automatically determines the optimum strategy for partitioning, and fine-grained and coarse-grained parallelization, for each specific IC design flow step to ensure the best quality of results (QoR) and turnaround time (TAT) for a specific layout. As a result, the Olympus-SoC system scales linearly as CPUs are added, enabling customers to complete even their largest designs on schedule.

"Leading-edge customers are increasingly turning to the Olympus-SoC solution to get the best quality of results and the shortest design times," said Joseph Sawicki, vice president and general manager for the design-to-silicon division at Mentor Graphics. "Other place-and-route tools boast multithreading and multitasking capability, but no other product has a parallel timing analysis engine at its core to deliver fast multi-corner multi-mode analysis and optimization, and this is ultimately what determines overall time to design closure. Successes on high-end SoC products demonstrate the Mentor difference and why customers are standardizing on our solution for their high-end products."

Task-oriented parallelism, an add-on option to the Olympus-SoC place-and-route system, is available now and is priced starting at $180K.