SLEC is the cornerstone of advanced system-level design flows, including those using high-level synthesis (HLS) tools such as Mentor Graphics' Catapult C and Forte Design Systems' Cynthesizer. The latest release of SLEC supports ac_fixed and cynw_fixed dataypes that are commonly used in wireless designs to model digital signal processing algorithms such as Fast Fourier Transforms and Reed Solomon decoders. SLEC comprehensively verifies the register transfer level (RTL) implementation generated by HLS without running time consuming simulations.

Similarly, SLEC supports ac_windows and external memory interfaces which simplify system-level modeling of computations on large frames data typical in H.264 codec and edge detection designs.

Used by design teams around the world, SLEC proves the functional equivalence between designs with sequential differences. By verifying that two designs produce the same output for all possible inputs, over all time, the quality of verification that SLEC performs in minutes is equal to years of running simulation. Because SLEC does not require testbenches or assertions, engineers spend significantly less time developing verification environments and more time creating innovative SoC solutions. The latest release of SLEC is shipping now and runs on Linux. For more details, contact Calypto at info@calypto.com.